|
Details, datasheet, quote on part number:NCV7310
| |
Datasheet text preview:
NCV7310 Single Wire LIN Transceiver with Regulator Control
N C V 7 3 1 0 provides the physical interface for LIN (Local Interconnect Network). The device works in cooperation with a microprocessor providing serial data to a single wire network, and receiving data over the same network. System design requires a master/slave operation. The device is backward compatible with ISO9141 while meeting the newer LIN objectives, including slew rate control. Applications can be found in the industrial market as well as the automotive market. This device includes an inhibit (INH) function used to control an external voltage regulator. Features · SingleWire Transceiver Compatible with the LIN Protocol · Also Compatible with ISO 9141 · 20 kbit/s Operation · Low Current Sleep Mode · Short Circuit Protection · Thermal Shutdown · ESD to 4.0 kV All Pins · Loss of Ground Does Not Affect Bus Activity · Unpowered Node Does Not Affect Bus Activity
http://onsemi.com
SO8 D SUFFIX CASE 751
PIN CONNECTION AND MARKING DIAGRAM
RxD EN VCC TxD 1 7310 ALYW 8 INH VS Bus GND
VS
INH
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
EN VCC VS 2 State Control RxD BUS Drive
ORDERING INFORMATION
Device NCV7310D NCV7310DR2 Package SO8 SO8 Shipping 95 Units/Rail 2500 Tape & Reel
GND Current Limit TxD Thermal Shutdown Wave Shaper
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2001
1
November, 2001 Rev. 5
Publication Order Number: NCV7310/D
NCV7310
VS Power Up
StandBy EN = LOW INH = HIGH RxD = LOW(1), HIGH(3) VCC = ON EN goes high Normal Mode EN = HIGH INH = HIGH VCC = ON Wake Up t > t[wake]
EN goes high VCC = ON
EN goes low Sleep Mode EN = LOW INH = FLOATING VCC = OFF(2)
1. After wakeup via bus. 2. ON when INH not used to control external voltage regulator. 3. After VS power up.
Figure 2. State Diagram
MAXIMUM RATINGS*
Symbol VCC VS Bus Bus EN, TxD, RxD INH ESD TJ Tstg R J C R J A Logic Power Supply Voltage Battery Supply Voltage Bus Input Voltage Bus Input Voltage (t < 1.0 ms) Logic Input Voltage INHIBIT ESD Discharge Susceptibility (Human Body Model) Operating Junction Temperature Storage Temperature Range Package Thermal Resistance JunctiontoCase JunctiontoAmbient Rating Value 0.3 to 6.0 0.3 to 40 20 to 28 40 0.3 to VCC + 0.3 0.3 to VS + 0.3 4.0 40 to 150 55 to 150 45 165 Unit V V Vdc V V V kV °C °C °C/W °C/W
*The maximum package power dissipation must be observed.
http://onsemi.com
2
NCV7310
ELECTRICAL CHARACTERISTICS (4.5 V VCC 5.5 V, 6.0 V VS 20 V, RT = 1.0 k, EN = VCC, 40°C TJ 125°C; unless otherwise specified. Note 1. See Figures 4 and 5.)
Characteristic ICC Quiescent Current Recessive State ICC Quiescent Current Dominant State IS Quiescent Current Recessive State IS Quiescent Current Dominant State Quiescent Current Sleep Mode RxD High Level Output Voltage RxD Low Level Output Voltage Receiver Threshold Voltage, recessive to dominant edge Receiver Threshold Voltage, dominant to recessive edge Receiver Hysteresis TxD High Level Threshold Voltage TxD Low Level Threshold Voltage TxD Hysteresis TxD Pull Up Current Bus Recessive Output Voltage Bus Dominant Output Voltage Bus Short Circuit Current Bus Leakage Current Bus Pull Up Resistance Bus Wakeup Threshold Voltage EN High Level Threshold Voltage EN Low Level Threshold Voltage EN Pull Down Resistance INH High Level Drop Voltage, INH = VS INH INH Leakage Current IINH = 0.15 mA Sleep Mode, INH = 0 V TxD = 0 V TxD = VCC TxD = 0 V Bus = 13.5 V VCC = 0 V, VS = 0 V, Bus = 12 V VCC = 0 V, VS = 0 V, Bus = 20 V Test Conditions TxD = VCC, Note 2. TxD = 0 V, Note 2. TxD = VCC TxD = 0 V VS 12 V. Note 3. IRxD = 400 µA IRxD = 400 µA Min 0.8 × VCC 0 0.4 × VS 0.3 × VCC 150 0.8 × VS 0 40 750 20 0.4 × VS 0.3 × VCC 15 5.0 Typ 2.0 2.0 1.0 6.0 35 0.46 × VS 0.54 × VS 0.08 × VS 0.5 × VCC +0.4 V 0.5 × VCC 0.4 V 800 100 VS 70 350 0 30 0.5 × VCC +0.4 V 0.5 × VCC 0.4 V 30 0.05 0 Max 4.0 4.0 2.0 8.0 50 VCC 0.2 × VCC 0.6 × VS 0.7 × VCC 80 0.2 × VS 110 5.0 47 0.7 × VS 0.7 × VCC 60 0.5 5.0 Unit mA mA mA mA µA V V V V V V mV µA V V mA µA k V V V k V µA
1. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 2. Sum of current into VCC and EN pins. 3. Sum of current into Bus and VS pins. VS = VBUS 12 V, IQ = IS + IBUS.
http://onsemi.com
3
|
|
