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Part: SG3525A
Category:
Power Management
-> PWM Controllers
-> Others
Description: Pulse Width Modulator Control Circuit
Company: ON Semiconductor
Datasheet: Download SG3525A datasheet File size : 611 kB
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SG3525A Pulse Width Modulator Control Circuit
The SG3525A pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The onchip +5.1 V reference is trimmed to ±1% and the error amplifier has an input commonmode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. This device also features builtin softstart circuitry, requiring only an external timing capacitor. A shutdown pin controls both the softstart circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as softstart recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the softstart capacitor when VCC is below nominal. The output stages are totempole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an offstate.
http://onsemi.com MARKING DIAGRAM
16 PDIP16 N SUFFIX CASE 648 16 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week 1 SG3525AN AWLYYWW
· · · · · · · · ·
8.0 V to 35 V Operation 5.1 V ± 1.0% Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses PulsebyPulse Shutdown Dual Source/Sink Outputs: ±400 mA Peak
PIN CONNECTIONS
Inv. Input Noninv. Input Sync OSC. Output CT RT Discharge
VC 13
1 2 3 4 5 6 7 8 (Top View)
16 Vref 15 VCC 14 Output B 13 VC 12 Ground 11 Output A 10 Shutdown 9 Compensation
Vref VCC Ground OSC Output Sync RT CT Discharge Compensation INV. Input Noninv. Input CSoft-Start Shutdown
16 15 12 4 3 6 5 7 9 1 2 8 10 Error Amp + Oscillator Reference Regulator
To Internal Circuitry
Soft-Start
Output A 11
UnderVoltage Lockout
NOR Q Q NOR
F/F
14 Output B
ORDERING INFORMATION
Device SG3525AN Package PDIP16 Shipping 25 Units/Rail
+ - PWM 50µA
S
R Latch S SG3525A Output Stage
VREF
5.0k
5.0k
Figure 1. Representative Block Diagram
© Semiconductor Components Industries, LLC, 2001
1
July, 2001 Rev. 3
Publication Order Number: SG3525A/D
SG3525A
MAXIMUM RATINGS (Note 1)
Rating Supply Voltage Collector Supply Voltage Logic Inputs Analog Inputs Output Current, Source or Sink Reference Output Current Oscillator Charging Current Power Dissipation (Plastic & Ceramic Package) TA = +25°C (Note 2) TC = +25°C (Note 3) Thermal Resistance JunctiontoAir Thermal Resistance JunctiontoCase Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) PD 1000 2000 R J A R J C TJ Tstg TSolder 100 60 +150 55 to +125 +300 °C/W °C/W °C °C °C IO Iref Symbol VCC VC Value +40 +40 0.3 to +5.5 0.3 to VCC ±500 50 5.0 Unit Vdc Vdc V V mA mA mA mW
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Collector Supply Voltage Output Sink/Source Current (Steady State) (Peak) Reference Load Current Oscillator Frequency Range Oscillator Timing Resistor Oscillator Timing Capacitor Deadtime Resistor Range Operating Ambient Temperature Range 1. Values beyond which damage may occur. 2. Derate at 10 mW/°C for ambient temperatures above +50°C. 3. Derate at 16 mW/°C for case temperatures above +25°C. Symbol VCC VC IO 0 0 Iref fosc RT CT RD TA 0 0.1 2.0 0.001 0 0 Min 8.0 4.5 Max 35 35 ±100 ±400 20 400 150 0.2 500 +70 mA kHz k µF °C Unit Vdc Vdc mA
APPLICATION INFORMATION
Shutdown Options (See Block Diagram, front page)
Since both the compensation and softstart terminals (Pins 9 and 8) have current source pullups, either can readily accept a pulldown signal which only has to sink a maximum of 100 µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM
latch is immediately set providing the fastest turnoff signal to the outputs; and a 150 µA current sink begins to discharge the external softstart capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the softstart capacitor, thus, allowing, for example, a convenient implementation of pulsebypulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turnon upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
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SG3525A
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics REFERENCE SECTION Reference Output Voltage (TJ = +25°C) Line Regulation (+8.0 V VCC +35 V) Load Regulation (0 mA IL 20 mA) Temperature Stability Total Output Variation Includes Line and Load Regulation over Temperature Short Circuit Current (Vref = 0 V, TJ = +25°C) Output Noise Voltage (10 Hz f 10 kHz, TJ = +25°C) Long Term Stability (TJ = +125°C) (Note 5) OSCILLATOR SECTION (Note 6, unless otherwise noted.) Initial Accuracy (TJ = +25°C) Frequency Stability with Voltage (+8.0 V VCC +35 V) Frequency Stability with Temperature Minimum Frequency (RT = 150 k, CT = 0.2 µF) Maximum Frequency (RT = 2.0 k, CT = 1.0 nF) Current Mirror (IRT = 2.0 mA) Clock Amplitude Clock Width (TJ = +25°C) Sync Threshold Sync Input Current (Sync Voltage = +3.5 V) ERROR AMPLIFIER SECTION (VCM = +5.1 V) Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain (RL 10 M) Low Level Output Voltage High Level Output Voltage Common Mode Rejection Ratio (+1.5 V VCM +5.2 V) Power Supply Rejection Ratio (+8.0 V VCC +35 V) PWM COMPARATOR SECTION Minimum Duty Cycle Maximum Duty Cycle Input Threshold, Zero Duty Cycle (Note 6) Input Threshold, Maximum Duty Cycle (Note 6) Input Bias Current DCmin DCmax Vth Vth IIB 45 0.6 49 0.9 3.3 0.05 0 3.6 1.0 % % V V µA VIO IIB IIO AVOL VOL VOH CMRR PSRR 60 3.8 60 50 2.0 1.0 75 0.2 5.6 75 60 10 10 1.0 0.5 mV µA µA dB V V dB dB fosc D VCC fosc DT fmin fmax ±2.0 ±1.0 ±0.3 ±6.0 ±2.0 % % Vref Regline Regload Vref/T Vref ISC Vn S 5.00 4.95 5.10 10 20 20 80 40 20 5.20 20 50 5.25 100 200 50 Vdc mV mV mV Vdc mA µVrms mV/khr Symbol Min Typ Max Unit
%
400 1.7 3.0 0.3 1.2
50 2.0 3.5 0.5 2.0 1.0
2.2 1.0 2.8 2.5
Hz kHz mA V µs V mA
4. Tlow = 0° Thigh = +70°C 5. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 6. Tested at fosc = 40 kHz (RT = 3.6 k, CT = 0.01 µF, RD = 0 ).
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