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Details, datasheet, quote on part number:SN74LS138
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Datasheet text preview:
SN74LS138 1-of-8 Decoder/ Demultiplexer
The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. · Demultiplexing Capability · Multiple Input Enable for Easy Expansion · Typical Power Dissipation of 32 mW · Active Low Mutually Exclusive Outputs · Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 0.4 8.0 Unit V °C mA mA
16 1
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LOW POWER SCHOTTKY
16 1
PLASTIC N SUFFIX CASE 648
SOIC D SUFFIX CASE 751B
16 1
SOEIAJ M SUFFIX CASE 966
ORDERING INFORMATION
Device SN74LS138N SN74LS138D SN74LS138DR2 SN74LS138M SN74LS138MEL Package 16 Pin DIP SOIC16 SOIC16 SOEIAJ16 SOEIAJ16 Shipping 2000 Units/Box 38 Units/Rail 2500/Tape & Reel See Note 1 See Note 1
1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2001
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October, 2001 Rev. 7
Publication Order Number: SN74LS138/D
SN74LS138
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 O0 15 O1 14 O2 13 O3 12 O4 11 O5 10 O6 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In Line Package. 1 A0 2 A1 3 A2 4 E1 5 E2 6 E3 7 O7 8 GND
LOADING (Note a) PIN NAMES A0 - A2 E1, E2 E3 O0 - O7 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC SYMBOL
123 456 1 23 A0 A1 A2 E
O0 O1 O2 O3 O4 O5 O6 O7
15 14 13 12 11 10 9 7 VCC = PIN 16 GND = PIN 8
LOGIC DIAGRAM
A2
3 2
A1
1
A0
4
E1 E2 E3
5 6
VCC = PIN 16 GND = PIN 8 = Pin Numbers
7
9
10
11
12
13
14
15
O7
O6
O5
O4
O3
O2
O1
O0
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SN74LS138
FUNCTIONAL DESCRIPTION
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky barrier diode process. The decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled provides eight mutually exclusive active LOW Outputs (O0O7). The LS138 features three Enable inputs, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable
function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter. (See Figure a.) The LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state.
TRUTH TABLE
INPUTS E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H OUTPUTS O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
A0 A1 A2 LS04 A3 A4 H 123 A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 O0 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 O31 123 E
Figure a
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