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Details, datasheet, quote on part number:82C465MV
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Datasheet text preview:
OPTi
®
82C465MV/MVA/MVB Single-Chip Mixed Voltage Notebook Solution Data Book
Revision: 3.0 912-3000-016 October, 1997
Copyright
Copyright © 1997, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to revise the design and associated documentation and to make changes from time to time in the content without obligation of OPTi Inc. to notify any person of such revisions or changes. Note: Before designing contact OPTi for latest Product Alerts, Applications Notes, and Errata for this product line.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
888 Tasman Drive Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 WWW : http://www.opti.com/
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82C465MV/MVA/MVB Table of Contents
1.0 2.0 Features .......... 1 Overview ......... 4
2.1 Upgrade Comparison ....... 4
3.0
Signal Definitions .... 5
3.1 3.2 3.3 Terminology/Nomenclature Conventions ....... 5 Pinout Options ... 5 Strap-Selected Interface Options ............ 5 3.3.1 3.3.2 3.3.3 3.3.4 3.4 Mixed Voltage Interface Options ........... 7 Resume Reset (RSMRST#) Function ... 7 Reading the 1X/2X Strap Setting........... 7 Using Strap Options with TTL Logic ...... 8
Program Selected Interface Options....... 9 3.4.1 3.4 .2 DACKMUX Decoder Lines Source ........ 9 EPMI Signal Source .... 10 3.4.2.1 Additional EPMI Sources ..... 10
3.5
Standard Mode 82C465MV Interface ..... 11 3.5.1 3.5.2 3.5.3 Reduced Memory Interface Signal Group Option........12 82C465MV Interface with L2 Cache Support ..... 14 82C465MV with 386 Interface .... 15
3.6 3.7
Pin Signal Characteristics ...... 16 Signal Descriptions ........ 21 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 Clock and Reset Interface .......... 21 CPU / VL-Bus Interface ........ 22 DRAM Interface ........... 25 L2 Cache Interface ...... 26 ISA Bus Interface.........26 IPC (82C206) Interface.........27 PMU Interface.....28
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82C465MV/MVA/MVB
Table of Contents (cont.)
3.7.8 3.7.9 Miscellaneous Signal Interface ............ 30 Power and Ground Pins ............. 31
4.0
Functional Description ........ 33
4.1 4.2 463/465 Chipset Programming Comparison .......... 33 CPU and VL-Bus Interface ...... 33 4.2.1 4.2.2 Basic Command Interface .......... 33 4.2.1.1 Cycle Signals ........ 33 Local Device Interface .......... 34 4.2.2.1 LDEV# Operation ........ 34 4.2.2.2 LRDY# Operation........35 4.2.2.3 VL-Bus Arbitration Logic ...... 35 VL-Bus Masters ........... 36 4.2.3.1 Hardware Considerations .... 36 4.2.3.2 Programming ........ 36 Data Bus Conversion/Data Path Logic ......... 36 4.2.4.1 CPU Data Bus Multiplex Option .......... 36 Numeric Coprocessor Interface...........37 4.2.5.1 Hardware Considerations .... 37 4.2.5.2 Programming ........ 37 Special CPU Interface Support............37 4.2.6.1 Ability to Cut CPU Power During Suspend .. 37 4.2.6.2 Programmable A20M# Functionality ............ 37 4.2.6.3 Programmable CPU RESET Functionality...38 4.2.6.4 Programmable DACK2# Functionality ......... 38 4.2.6.5 Cyrix Linear Burst Mode Support ........ 38 4.2.6.6 Programmable Exclusion of Coprocessor Recognition........38 4.2.6.7 Programmable RDYI# Functionality....38
4.2.3
4.2.4 4.2.5
4.2.6
4.3
System Functions ........... 39 4.3.1 Reset Logic.........39 4.3.1.1 RST1# .......... 39 4.3.1.2 RST4# .......... 39 4.3.1.3 CPURST and SRESET........39 4.3.1.4 Resume Reset (RSMRST#) Function .......... 39 4.3.1.5 Rapid RESET Generation .... 41 4.3.1.6 Fast Reset Handling in SMM ........ 41
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912-3000-016 Revision: 3.0
82C465MV/MVA/MVB
Table of Contents (cont.)
4.3.2 System Clock Generation ........... 42 4.3.2.1 Input Clocks .......... 42 4.3.2.2 Output Clocks ............. 43 A20M# Generation ...... 45 4.3.3.1 Rapid A20M# Generation .... 45 4.3.3.2 Inhibition of Fast A20M# and Fast Reset Generation .......... 46 4.3.3.3 A20M# Handling in SMM ..... 47 4.3.3.4 Port 060/064h A20M# Setting Accessibility .......... 47
4.3.3
4.4
DRAM Controller .... ......... 48 4.4.1 4.4.2 4.4.3 DRAM Controller Hardware Options ... 48 DRAM Bus Drive Capability........50 Setting Up DRAM Operation ...... 50 4.4.3.1 Faster Memory Cycles ......... 52 4.4.3.2 DRAM Mapping Scheme Enable ........ 52 4.4.3.3 DRAM Control Register 2I - SYSCFG 35h .. 52 EDO DRAM Support....53 DRAM Cycle Speed.....53 System ROM and Shadow RAM ......... 54
4.4.4 4.4.5 4.4.6 4.5
Cache Control .. 57 4.5.1 4.5.2 Global Enabling of Cacheability...........57 Defining Non Cacheable Blocks .......... 57 4.5.2.1 C000, E000, F000h Block Cache Enable .... 58 4.5.2.2 Cache Control of C000-F000h ...... 59 4.5.2.3 Cache Invalidation Feature .. 61 L1 Write-Back Cache Support .... 61 4.5.3.1 Hardware Considerations .... 61 4.5.3.2 Extra Programmable Pin Options ....... 62 4.5.3.3 Programming ........ 63 4.5.3.4 Burst Write Feature ..... 63 L2 Cache Support........64 4.5.4.1 Performance ......... 65 4.5.4.2 L2 Cache Operation Details .......... 65 4.5.4.3 L2 Cache Arrangement ........ 67 4.5.4.4 Differences Between L2 Support and No Cache Support Modes ....... 68 4.5.4.5 Hardware Considerations .... 69 4.5.4.6 Programming ........ 69 4.5.4.7 Timing Control Register ....... 70
4.5.3
4.5.4
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