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Details, datasheet, quote on part number:0X9160
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Datasheet text preview:
OX9160 PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus
FEATURES
· · · · · · · 33MHz, 32-bit target PCI controller. Fully PCI 2.2 and PCI Power Management 1.0 compliant. 8- or 32-bit pass-through Local bus. IEEE1284 parallel port. Parallel port supports EPP mode for maximum data transfer rate to printers, removable drives etc. Most operations complete within one PCI frame (no retries). Supports shared interrupts · · · · · · · · · 12 multi-purpose I/O pins which can be configured as interrupt input pins. EEPROM interface for optional reconfiguration. Local bus operation via I/O or memory mapping. Local bus supports Intel or Motorola mode signalling. Existing driver support for common I/O solutions. On-chip oscillator. 5.0V operation. Low power CMOS. 160 TQFP package.
DESCRIPTION
The OX9160 is a low-cost, general purpose PCI bridge solution designed to ease the migration to PCI of parallel port cards and instrumentation devices. It is configurable to provide either a Local bus interface or a bi-directional parallel port. Using the local bus function, legacy devices can be easily accessed throught the target PCI interface, which is compliant with version 2.2 of the PCI Bus Specification and version 1.0 of PCI Power Management Specification. All reads and writes are completed with a minimum of PCI wait states, which ensures lower PCI bus occupancy than most similar PCI bridge solutions. The local bus can be configured to operate with either 8- or 32-bit data, using either Intel x86 style or Motorola style signalling. Alternatively the local bus can be disabled in favour of an integrated IEEE 1284 EPP parallel port. The parallel port is an IEEE 1284-compliant host interface, which supports SPP, PS2 (bidirectional) and EPP modes. The local Bus function is extremely flexible, allowing the designer to customize the addressable space, divide it into chip-select regions, access devices via I/O or memory space mapping, and adjust the timings of all operations. The default register values have been selected to support many standard peripheral chips such as I/O controllers and other ISA-type devices, however all such parameters can be overwritten using an optional MicrowireTM serial EEPROM.
Oxford Semiconductor Ltd. 69 Milton Park, Abingdon, Oxon, OX14 4RX, UK Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999 OX9160 Data Sheet Revision 1.1 Feb. 1999 Part No. OX9160-TQC33-A
OXFORD SEMICONDUCTOR LTD.
OX9160
CONTENTS
1 2 3 4
4.1 4.2 4.2.1 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.6
BLOCK DIAGRAM ..... 3 PIN INFORMATION .... 4 PIN DESCRIPTIONS .. 5 PCI TARGET CONTROLLER ............ 8
OPERATION ...... 8 CONFIGURATION SPACE......... 8 PCI CONFIGURATION SPACE REGISTER MAP........... 9 ACCESSING LOGICAL FUNCTIONS ...... 10 PCI ACCESS TO 8-BIT LOCAL BUS.... 10 PCI ACCESS TO 32-BIT LOCAL BUS........... 11 PCI ACCESS TO PARALLEL PORT .... 11 ACCESSING LOCAL CONFIGURATION REGISTERS .... 12 LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ..... 12 MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04) ......... 13 LOCAL BUS TIMING PARAMETER REGISTER 1 `LT1' (OFFSET 0X08):...... 14 LOCAL BUS TIMING PARAMETER REGISTER 2 `LT2' (OFFSET 0X0C): ..... 16 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X1C) ............ 17 PCI INTERRUPTS ........... 18 POWER MANAGEMENT.......... 19 OVERVIEW ...... 20 OPERATION .... 20 CONFIGURATION & PROGRAMMING.... 21 CLOCK REFERENCES ............ 21 OPERATION AND MODE SELECTION ............ 22 SPP MODE ........ 22 PS2 MODE... 22 EPP MODE ........ 22 ECP MODE (NOT SUPPORTED) ........ 22 PARALLEL PORT INTERRUPT .............. 22 REGISTER DESCRIPTION....... 23 PARALLEL PORT DATA REGISTER `PDR' .. 23 DEVICE STATUS REGISTER `DSR' .... 23 DEVICE CONTROL REGISTER `DCR'.......... 24 EPP ADDRESS REGISTER `EPPA' ..... 24 EPP DATA REGISTERS `EPPD1-4' ..... 24 EXTENDED CONTROL REGISTER `ECR' .... 24 SPECIFICATION ............. 25 EEPROM DATA ORGANISATION........... 25 ZONE0: HEADER........ 25 ZONE1: LOCAL CONFIGURATION REGISTERS......... 26 ZONE2: IDENTIFICATION REGISTERS ....... 27 ZONE3: PCI CONFIGURATION REGISTERS ........ 27
5
5.1 5.2 5.3 5.4
LOCAL BUS.....20
6
6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6
BIDIRECTIONAL PARALLEL PORT ............. 22
7
7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4
SERIAL EEPROM.....25
8 9
OPERATING CONDITIONS....28 DC ELECTRICAL CHARACTERISTICS........28
Page 2
Data Sheet Revision 1.1
OXFORD SEMICONDUCTOR LTD.
9.1 9.2
OX9160
NON-PCI I/O BUFFERS............ 28 PCI I/O BUFFERS ........... 29
10
10.1 10.2
AC ELECTRICAL CHARACTERISTICS .... 30
PCI BUS........... 30 LOCAL BUS..... 30
11 12 13
TIMING WAVEFORMS ........ 32 PACKAGE INFORMATION..........37 ORDERING INFORMATION ........ 37
1
BLOCK DIAGRAM
LBA[7:0] LBD[7:0] Local Bus AD[31:0] C/BE[3:0]# CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA# PCI interface Internal Data / control bus ACK# PE BUSY Parallel port SLCT ERR# SLIN# INIT# AFD# STB# PD[7:0] LBCS[3:0] LBWR# LBRD# LBRST
MODE[1:0]
Config. interface
PME# Interrupt logic EEPROM interface XTALI XTALO UART_Ck_Out Crystal Oscillator LBCLK MIO[11:0]
EE_DO EE_DI EE_CK EE_CS
Figure 1 : OX9160 block diagram
Data Sheet Revision 1.1
Page 3
OXFORD SEMICONDUCTOR LTD.
OX9160
2
PIN INFORMATION
Mode `00': 8-bit local bus
LBA1 LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 VDD GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 GND GND GND GND GND NC NC
LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
OX9160-TQC33-A
NC NC NC NC GND GND GND GND VDD XTL_Ck_Out GND GND GND GND GND VDD XTLO XTLI GND GND GND NC NC VDD GND NC NC NC NC GND GND GND GND GND GND Mode0 Mode1 NC EE_DI EE_CK
Mode `01': Parallel port
BUSY SLCT ERR# NC NC NC NC NC NC VDD GND NC SLIN# INIT# AFD# STB# VDD GND NC PD0 PD1 PD2 PD3 VDD GND PD4 PD5 PD6 PD7 MIO8 MIO9 MIO10 MIO11 GND GND GND GND GND NC NC PE ACK# NC MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 NC INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Mode `11': 32-bit local bus
LBA1 LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 VDD GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 LBD8 LBD9 LBD10 LBD11 LBD12 LBD13 LBD14
OX9160-TQC33-A
LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OX9160-TQC33-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LBD15 LBA8 LBA9 LBA10 LBA11 NC NC NC VDD XTL_Ck_Out GND NC LBD16 LBD17 LBD18 VDD XTLO XTLI GND LBD19 LBD20 LBD21 LBD22 VDD GND LBD23 LBD24 LBD25 LBD26 LBD27 LBD28 LBD29 LBD30 LBD31 GND Mode0 Mode1 NC EE_DI EE_CK
NC NC NC NC GND GND GND GND VDD NC GND GND GND GND GND VDD NC NC GND GND GND NC NC VDD GND NC NC NC NC GND GND GND GND GND GND Mode0 Mode1 NC EE_DI EE_CK
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Data Sheet Revision 1.1
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2: Pinout in all configurable modes (package = 160 TQFP)
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Page 4
OXFORD SEMICONDUCTOR LTD.
OX9160
3
PIN DESCRIPTIONS
Dir 11 P_I/O AD[31:0] Multiplexed PCI Address/Data bus Name Description
Mode 00 01 PCI Interface
139, 140, 141, 143, 144, 145, 148, 149, 152, 154, 155, 156, 159, 160, 1, 2, 14, 15, 16, 19, 20, 23, 24, 26, 28, 29, 32, 33, 34, 36, 37, 38
150, 3, 13, 27 136 4 7 5 6 9 12 11 10 151 134 132 138 Local bus 122 N/A 122 123 N/A 123 102 114-7 112 113
105-8 118-21
P_I P_I P_I P_O P_I P_O P_O P_I/O P_O P_I/O P_I P_I P_OD P_OD O O O O O O O O Z O O I/O I/O
C/BE[3:0]# CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA # PME# LBRST LBRST# LBDOUT LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBA[12:0] LBD[7:0] LBD[31:0]
PCI Command/Byte enable PCI system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialization device select PCI system reset PCI interrupt Power management event Local bus active-high reset Local bus active-low reset Local bus data out enable. This pin can be used by external transceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode. Local bus active-low Chip-Select (Intel mode) Local bus active-low Data-Strobe (Motorola mode) Local bus active-low write-strobe (Intel mode) Local bus Read-not-Write control (Motorola mode) Local bus active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) (8-bit mode) Local bus address signals (32-bit mode) Local bus address signals (8-bit mode) Local bus data signals (32-bit mode) Local bus data signals
N/A N/A N/A N/A N/A N/A N/A
114-7 112 113 N/A
76-9, 105-8, 118-21
N/A
92-5 98-101
N/A
47-55, 58-61, 66-68, 80-87, 92-95, 98-101
N/A
Data Sheet Revision 1.1
Page 5
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