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Details, datasheet, quote on part number:OX9162
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| Part: | OX9162 |
| Category: | Interface and Interconnect => PCI |
| Description: | Integrated Parallel Port/local Bus And Pci Interface. |
| Company: | Oxford Micro Devices, Inc. |
| Datasheet: | Download OX9162 datasheet File size : 527 kB |
| Request For quote: | Find where to buy OX9162
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Datasheet text preview:
FEATURE
· · · 8 bit pass-through local bus IEEE1284 SPP/EPP/ECP parallel port Single function target PCI controller, fully PCI 2.2 and PCI Power Management 1.0 compliant
OX9162 Integrated Parallel Port/Local Bus and PCI interface
· · · · 2 multi-purpose IO pins which can be configured as interrupt input pins Can be reconfigured using optional non-volatile configuration memory (EEPROM) 5.0V operation 128 TQFP package
DESCRIPTION
The OX9162 is a single chip solution for PCI-based parallel expansion add-in cards, or local bus bridges. It is a single function PCI device, where function 0 offers either an 8 bit Local Bus or a bi-directional parallel port. For legacy applications the PCI resources are arranged so that the parallel port can be located at standard I/O addresses. The efficient 32-bit, 33MHz target-only PCI interface is compliant with version 2.2 of the PCI Bus Specification and version 1.0 of PCI Power Management Specification. For full flexibility, all the default register values can be overwritten using an optional MicrowireTM serial EEPROM. Bridging applications can be realised using the 8-bit passthrough Local Bus function. The addressable space can be increased up to 256 bytes for each chip-select region. The OX9162 alternatively provides an IEEE1284 EPP/ECP parallel port which fully supports the existing Centronics interface. The parallel port can be enabled in place of the Local Bus.
Oxford Semiconductor Ltd. 69 Milton Park, Abingdon, Oxon, OX14 4RX, UK Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999 OX9162 1.0 PRELIMINARY October 1999 Part No. OX9162-TQC-A
OXFORD SEMICONDUCTOR LTD.
OX9162
6.3 REGISTER DESCRIPTION.......... 22 6.3.1 PARALLEL PORT DATA REGISTER `PDR'... 22 6.3.2 ECP FIFO ADDRESS / RLE .... 22 6.3.3 DEVICE STATUS REGISTER `DSR' ..... 22 6.3.4 DEVICE CONTROL REGISTER `DCR'.. 23 6.3.5 EPP ADDRESS REGISTER `EPPA' ...... 23 6.3.6 EPP DATA REGISTERS `EPPD1-4' ...... 23 6.3.7 ECP DATA FIFO..... 23 6.3.8 TEST FIFO........ 23 6.3.9 CONFIGURATION A REGISTER........... 23 6.3.10 CONFIGURATION B REGISTER........... 24 6.3.11 EXTENDED CONTROL REGISTER `ECR' .... 24
CONTENTS
1 2 3 4 PIN INFORMATION..3 PIN DESCRIPTIONS ......... 4 CONFIGURATION & OPERATION...8 PCI TARGET CONTROLLER...........9
4.1 OPERATION...9 4.2 CONFIGURATION SPACE ... 9 4.2.1 PCI CONFIGURATION SPACE REGISTER MAP 10 4.3 ACCESSING LOGICAL FUNCTIONS........11 4.3.1 PCI ACCESS TO 8-BIT LOCAL BUS ..... 11 4.3.2 PCI ACCESS TO PARALLEL PORT ...... 11 4.4 ACCESSING LOCAL CONFIGURATION REGISTERS ...... 12 4.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ... 12 4.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04)....13 4.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 `LT1' (OFFSET 0X08): ..... 13 4.4.4 LOCAL BUS TIMING PARAMETER/BAR SIZING REGISTER 2 `LT2' (OFFSET 0X0C):..........15 4.4.5 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X10)........16 4.5 PCI INTERRUPTS.......17 4.6 POWER MANAGEMENT.....18 4.6.1 POWER MANAGEMENT USING MIO ... 18
7
7.1 SPECIFICATION......... 25 7.2 EEPROM DATA ORGANISATION.... 25 7.2.1 ZONE0: HEADER............ 25 7.2.2 ZONE1: LOCAL CONFIGURATION REGISTERS...... 27 7.2.3 ZONE2: IDENTIFICATION REGISTERS........ 28 7.2.4 ZONE3: PCI CONFIGURATION REGISTERS28 7.2.5 ZONE4: FUNCTION ACCESS....... 28
SERIAL EEPROM .. 25
8 9
9.1 9.2
OPERATING CONDITIONS............ 30 DC ELECTRICAL CHARACTERISTICS .. 30 AC ELECTRICAL CHARACTERISTICS 32
NON-PCI I/O BUFFERS ...... 30 PCI I/O BUFFERS....... 31
10
10.1 10.2
PCI BUS ....... 32 LOCAL BUS.......... 32
5
5.1 5.2 5.3
LOCAL BUS .......... 19
11
TIMING WAVEFORMS ...... 34
OVERVIEW...19 OPERATION..........19 CONFIGURATION & PROGRAMMING ..... 20 OPERATION AND MODE SELECTION.....21 SPP MODE........21 PS2 MODE ........ 21 EPP MODE........21 ECP MODE........21 PARALLEL PORT INTERRUPT .. 21
12 ERRATA 1 IMMEDIATE POWER DOWN FILTERING........ 39
6
6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2
BI-DIRECTIONAL PARALLEL PORT...... 21
Data Sheet Revision 1.1 PRELIMINARY
Page 2
OXFORD SEMICONDUCTOR LTD.
OX9162
1
PIN INFORMATION
LBRD - ACK# LBA3-SLIN# LBA6-BUSY LBA4-ERR# LBA5-SLCT LBA1-AFD# LBA2-INIT#
128 pin TQFP LBD0-PD0 LBD1-PD1 LBD2-PD2 LBD3-PD3 LBD4-PD4 LBD5-PD5 LBD6-PD6 LBD7-PD7 LBA0-STB DATA_EN LBA7-PE
GND ac
GND dc
GND ac
GND ac
VDD dc
VDD ac
EE_DO
EE_CS
LBCS0
EE_DI
TEST
96 NC EE_SK LBCS1 97
92
88
84
80
76
72
68
65 64 NC LBWR LBRST
NC 100 LBCLK NC NC MIO1 NC NC MODE NC Z_INTA Z_RESET G N D dc PCI_CLK V D D dc Z_PME AD31 NC AD30 AD29 G N D ac AD28 AD27 AD26 G N D ac V D D ac AD25 AD24 Z_CBE3 NC 60
MIO0
NC
NC
LBRST#
104 56
108 52
112 48
116 44
120 40
124 36
128 1 IDSEL AD23 NC 4 GND ac AD22 AD21 AD20 8 GND ac VDD ac AD19 AD18 12 Z_FRAME Z_CBE2 AD17 AD16 16 Z_TRDY Z_IRDY GND dc VDD dc 20 Z_DEVSEL Z_PERR Z_STOP GND ac 24 Z_SERR Z_CBE1 AD15 PAR 28 GND ac VDD ac AD14 AD13 32 NC
33
NC AD0 AD1 G N D ac AD2 AD3 V D D dc G N D dc NC NC AD4 AD5 G N D ac V D D ac AD6 AD7 NC NC Z_CBE0 AD8 G N D ac AD9 AD10 NC NC AD11 AD12 NC
Data Sheet Revision 1.1 PRELIMINARY
Page 3
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