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Part: EPF8017GH
Category:
Description: 10/100 Interface Module With Enhanced Common Mode Attenuation
Company: PCA Electronics Inc.
Datasheet: Download EPF8017GH datasheet File size : 188 kB
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Datasheet text preview:
10/100 Interface Module with Enhanced Common Mode Attenuation
ELECTRONICS, ELECTRONICS, INC.
EPF8017GH
· Optimized for DP83840A/DP83223 Chip Set · · Recommended for use with ICS 1890 Series and SSI78Q2120 · when connected per appropriate schematic · Guaranteed to operate with 8mA DC bias at 70°C · · Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards ·
Electrical Parameters @ 25°C
OCL @ 70°C 100KHz, 0.1Vrms 8mA DC Bias Cable Side 350µH 1-80 MHz Xmit -1 Rcv -1 Insertion Loss (dB Max.) 80-100 MHz Xmit -2 Rcv -2 100-150 MHz Xmit -3.5 Rcv -3 1-30 MHz Xmit -18 -18 Return Loss (dB Min.) 30-60 MHz Rcv -12 -12 60-100 MHz Xmit -10 -10 1-30 MHz Rcv -40 -40 Common Mode Rejection (dB Min.) 30-100 MHz Xmit -35 Rcv -30 100-500 MHz Xmit -10 Rcv -10 -35 -35 Crosstalk (dB Min.) [Between Channels] 5-10 MHz 10-100 MHz
Rcv Xmit
Rcv Xmit
· Isolation : 1500Vrms · Rise Time : 3.0nS Max. · Impedance : 100 · Receive Channel
Schematic
Transmit Channel
1
7 5
15 14 CMC
11
2 1:1 3
6
16 1:1
10 12
Package
A J Pin 1 I.D.
PCA EPF8017GH D.C.
Dimensions
N
Dim. A B C D E F G H I J K L M N P Q Min. .970 .380 .234 --.010 --.490 .017 .008 --0° .025 --------(Inches) Max. .990 .400 .252 --.015 --.510 .022 .013 --8° .045 --------(Millimeters) Nom. Min. Max. Nom. .980 24.64 25.15 24.89 .390 9.91 9.65 10.16 .247 6.30 5.94 6.40 .700 17.78 ----.013 .330 .254 .381 .100 2.54 ----.500 12.45 12.95 12.70 .020 .508 .432 .559 .011 .279 .203 .330 .140 3.56 ----4° 4° 0° 8° .035 .889 .635 1.14 .030 .762 ----.100 2.54 ----.092 2.34 ----.560 14.22 -----
B
Q
Solder Pad Layout
P
D
M
E C H F
K
L G
I
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8017GHa
Rev. A2 2/27/01
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
ELECTRONICS, ELECTRONICS, INC.
10/100 LAN Interface Module with Enchanced Common Mode Attenuation EPF8017GH
The circuit below is a guideline for interconnecting PCA's EPF8017GH with National DP83840A and DP83223 twister chip set for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Please consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective application notes. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15. Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please consult with the PCA Technical support group. This solution is similar to approaches used in EPF8013GM, EPF8022G and EPF8038S (a repeater interface module). It is recommended that system designers do not use the receiver side center tap to ground, via a capacitor. This may w o r s e n EMI, specifically if the secondary "common mode termination" is pulled to chassis ground as shown. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. The "common mode termination" load of 75 shown from the center taps of the secondary may be taken to chassis ground via a cap of suitable value. This depends upon user's design, EMI margin etc. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8017GH. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50, balanced and well coupled to achieve minimum radiation from these traces.
Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes)
0.10µF {Note 1} +
1
Receive
7
75 50
8 7 6 5 4
75
RXD
1000pF 12.1 0.1µF {Note 1}
2
5 6 10
50
+
RJ45*
CMT
TXU
-
12.1
16 14
12.1
3 2
2000V
12 11
1000pF +
15
12.1
Transmit
TXO PMRD
1 Node Pinout
TD
-
EPF8017GH
Isolation Cap
RXI
DP83840
DP83223
SD PMID
Chassis Ground
+
SD
+
Other pull down/up resistors not shown, for clarification please refer to National's application notes. Notes: 1. See text above for clarification. 2. *NIC side is shown. Hub side connections wiil have crossover swapping pins 3-6 & 1-2.
CSF8017GHb Rev. A2 2/27/01
RD
-
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pcainc.com
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