|
Details, datasheet, quote on part number:P4C116-35SC
| |
| Part: | P4C116-35SC |
| Category: | Memory => SRAM => SRAM |
| Description: | Org = 2K X 8 ;; Features. = Common I/o ;; ;; Taa (ns) = 10 to 35 ;; Package / Pins Dip = 24 ;; Package / Pins Soj = 24 ;; Package / Pins Soic / Sop = 24 |
| Company: | Performance Semiconductor Corp. |
| Datasheet: | Download P4C116-35SC datasheet File size : 78 kB |
| Request For quote: | Find where to buy P4C116-35SC
|
| |
Datasheet text preview:
P4C116
P4C116 ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 10/12/15/20/25/35 ns (Commercial) 15/20/25/35 ns (Military) Low Power Operation 633/715 mW Active -- 15, 20 550/633 mW Active -- 25, 35 193/220 mW Standby (TTL Input) Output Enable Control Function Single 5V±10% Power Supply Common Data I/O Fully TTL Compatible Inputs and Outputs Produced with PACE II TechnologyTM Standard Pinout (JEDEC Approved) 24-Pin 300 mil DIP, SOIC, SOJ 24-Pin Rectangular LCC (300 x 400 mils) 28-Pin Square LCC (450 x 450 mils)
DESCRIPTION
The P4C116 is a 16,384-bit ultra high-speed static RAMs organized as 2K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 633 mW active, 193 mW standby. The P4C116 is available in 24-pin 300 mil DIP, SOJ and SOIC packages providing excellent board level densities. The P4C116 is also available in 24-pin rectangular and 28-pin square LCC packages.
FUNCTIONAL BLOCK DIAGRAM
A (6) A I/O 1
INPUT DATA CONTROL COLUMN I/O ROW SELECT 16,384-BIT MEMORY ARRAY
PIN CONFIGURATIONS
A0 A1 A2 A3 A4 A5 A6 A7 I/O 1 I/O 2 I/O 3 G ND
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
V CC A10 A9 WE OE A8 CE I/O8 I/O7 I/O6 I/O5 I/O4
I/O 8
COLUMN SELECT
WE CE OE
A
(5)
A
DIP (P4, D4), SOJ (J4), SOIC (S4) DIP (P4 , D4), SOJ (J3 ), SOIC (S4 ) TOP VIEW
T O P VIEW
See Selection Guide Page for LCC
Means Quality, Service and Speed
1Q97
47
P4C116
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value 0.5 to +7 0.5 to VCC +0.5 55 to +125 Unit V Symbol TBIAS TSTG V °C PT I OUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value 55 to +125 65 to +150 1.0 50 Unit °C °C W mA
VTERM TA
RECOMMENDED OPERATING CONDITIONS
Grade(2) Commercial Ambient Temp 0°C to 70°C Gnd 0V Vcc 5.0V ±10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF
Output Capacitance VOUT= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) P4C116 Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO I CC I CC I CC ISB ISBI Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current Dynamic Operating Current 10, 12 Dynamic Operating Current 15, 20 Dynamic Operating Current 25, 35 Standby Power Supply Current (TTL Input Levels) VCC = Min., IIN = 18 mA IOL = +8 mA, VCC = Min. IOH = 4 mA, VCC = Min. VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC VCC = Max., f = Max., Outputs Open VCC = Max., f = Max., Outputs Open VCC = Max., f = Max., Outputs Open CE VIH, VCC = Max., f = Max., Outputs Open
___ ___
Test Conditions
Min 2.2 0.5 0.5
(3)
Max VCC +0.5 0.8 VCC+0.5 0.2 1.2 0.4
Unit V V V V V V V
VCC0.2
(3)
2.4 5 5 +5 +5 130 115 100 35 17
µA µA mA mA mA mA mA
___ ___
Standby Power Supply CE VHC, VCC = Max., f = 0, Outputs Open Current (CMOS Input Levels) VIN VLC or VIN VHC
48
P4C116
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial Military 10 180 N/A 12 170 N/A 15 160 170 20 155 160 25 150 155 35 140 150 Unit mA mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. t RC t AA t AC t OH tLZ t HZ t OE t OLZ t OHZ t PU t PD
Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down
10
12
15
20
25
35
Unit ns
Min Max Min Max Min Max Min Max Min Max Min Max 10 10 10 2 2 5 6 0 6 0 10 0 12 0 7 0 15 2 2 6 8 0 8 0 20 12 12 12 2 2 7 10 0 9 0 20 15 15 15 2 2 8 10 0 12 0 25 20 20 20 2 3 10 15 0 15 25 25 25 2 3 15 20 35 35 35 ns ns ns ns ns ns ns ns ns ns
OE TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
t RC ADDRESS t AA OE t OE CE t OLZ (8) t AC t LZ (8) DATA OUT t OHZ(8) t HZ(8) t OH
(9)
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than 3.0V and 100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address.
49
|
|
