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Details, datasheet, quote on part number:P4C1256-25C
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| Part: | P4C1256-25C |
| Category: | Memory => SRAM => SRAM |
| Description: | Org = 32K X 8 ;; Features. = Common I/o ;; ;; Taa (ns) = 12 to 35 ;; Package / Pins Dip = 28 ;; Package / Pins Soj = 28 ;; Package / Pins Soic / Sop = |
| Company: | Performance Semiconductor Corp. |
| Datasheet: | Download P4C1256-25C datasheet File size : 92 kB |
| Request For quote: | Find where to buy P4C1256-25C
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Datasheet text preview:
P4C1256
P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times) -- 12/15/20/25/35 ns (Commercial) -- 15/20/25/35/45 ns (Industrial) -- 20/25/35/45/55/70 ns (Military) Low Power -- 880 mW Active (Commercial) Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE CE OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages --28-Pin 300 mil DIP and SOJ --28-Pin 600 mil Ceramic DIP --28-Pin LCC(350 mil x 550 mil) --32-Pin LCC (450 mil x 550 mil)
DESCRIPTION
T h e P4C1256 is a 262,144-bit high-speed CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1256 is a member of a family of PACE RAMTM products offering fast access times. The P4C1256 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P4C1256 include 28-pin 300 mil DIP and SOJ packages. For military temperature range, Ceramic DIP and LCC packages are available.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
·· ·
PIN CONFIGURATIONS
VCC A2 A1
A0 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC
(8) A
262,144-BIT MEMORY ARRAY
WE
A14 A13 A12
A2 A3 A4 A5
4
3
A0
2 1
NC
A3 A4 A5 A6 A7 A8 A9 NC I/O1
5 6 7 8 9 10 11 12
32 31 30 29 28 27 26 25 24 23 22
WE A14
A 13 A 12 A 11 NC OE A 10 CE I/O8 I/O7
I/O 1
··· ··· ··· ···
A 11 OE A 10 CE I/0 8 I/0 7 I/0 6 I/0 5 I/0 4
A6
COLUMN I/O
INPUT DATA CONTROL
A7 A8 A9
· ··
···
I/O 2
I/01 I/02
COLUMN SELECT
13 21 14 15 16 17 18 19 20
GND I/O2 I/O3 I/O4 I/O5 I/O6 NC
I/03 GND
WE
··· ···
CE OE
A
(7)
A
DIP (P5, C5, D5-1), SOJ (J5) TOP VIEW
1519B
32 LCC (L6) TOP VIEW
See Selection Guide page for 28-pin LCC
Means Quality, Service and Speed
1Q97
117
P4C1256
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value 0.5 to +7 0.5 to VCC +0.5 55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value 55 to +125 65 to +150 1.0 50 Unit °C °C W mA
VTERM TA
V °C
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 5.0V ± 10%
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 8 10 pF pF
55°C to +125°C 40°C to +85°C Industrial Commercial 0°C to +70°C
Output Capacitance VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +8 mA, VCC = Min. IOH = 4 mA, VCC = Min. VCC = Max. VIN = GND to VCC Mil. Ind./Com'l. 2.4 10 5 10 5 ___ ___ ___ ___ +10 +5 +10 +5 45 30 20 10 Test Conditions P4C1256 Min Max 2.2
(3)
Unit V V V V V V µA µA
VCC +0.5
0.8 0.5 VCC 0.2 VCC +0.5 0.5
(3)
0.2 0.4
Output Leakage Current
VCC = Max., CE = VIH, Mil. VOUT = GND to VCC Ind./Com'l.
CE VIH or Mil. Standby Power Supply Current (TTL Input Levels) CE2 VIL, VCC= Max Ind./Com'l. f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE VHC or Mil. CE2 VLC, VCC= Max Ind./Com'l. f = 0, Outputs Open VIN VLC or VIN VHC
mA
ISB1
mA
n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than 3.0V and 100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested.
118
P4C1256
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter Temperature Range Commercial Military 12 170 N/A N/A 15 160 170 N/A 20 155 165 170 25 150 160 165 35 145 155 160 45 N/A 150 155 55 N/A N/A 150 70 N/A N/A 150 Unit mA mA mA
ICC
Dynamic Operating Current* Industrial
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. tRC tAA tAC tOH tLZ tHZ tOE
Parameter
-12
-15 15
-20 20
-25 25
-35 35
-45 45
-55 55
-70 70
Unit ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Read Cycle Time 12 Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 12 0 5 0 15 2 2 5 5 12 12 2 2 8 7
15 15 2 2
20 20 3 3 9 9
25 25 3 3 11 10
35 35 3 3 15 15
45 45 3 3 20 20
55 55 3 3 25 25
70 70
ns ns ns ns
30 30
ns ns
tOLZ tOHZ tPU tPD
0 7
0 9 0 20
0 11 0 20
0 15 0 20
0 20 0 25
0 25 0 30
0 30 0 35
ns ns ns ns
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