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Details, datasheet, quote on part number:P93U422-35DM
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| Part: | P93U422-35DM |
| Category: | Memory => SRAM => SRAM |
| Description: | Org = 256 X 4 ;; Features. = . ;; ;; Taa (ns) = 35 ;; Package / Pins Dip = 22 ;; Package / Pins Soj = . ;; Package / Pins Soic / Sop = 24 |
| Company: | Performance Semiconductor Corp. |
| Datasheet: | Download P93U422-35DM datasheet File size : 50 kB |
| Request For quote: | Find where to buy P93U422-35DM
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Datasheet text preview:
P93U422
P93U422 HIGH SPEED 256 x 4 STATIC CMOS RAM
FEATURES
Universal 256 x 4 Static RAM One part, the 93U422, replaces the following bipolar and CMOS parts: 93422A 93422 93L422A 93L422 Fast Access Time 35 ns (Commercial) 35 ns (Military) Standard 400 mil DIP and Chip carrier packages CMOS for Low Power 440 mW (Commercial) 495 mW (Military) 5V Power Supply ±10% for both commercial and military temperature ranges Separate I/O Fully static operation with equal access and cycle times Resistant to single event upset and latchup due to advanced process and design improvements
DESCRIPTION
The P93U422 is a 1,024-bit high-speed Static RAM with a 256 x 4 organization. The P93U422 is a universal device designed to replace the entire 93 and 93L 256 x 4 static RAM families. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and active HIGH chip select two (CS 2) as well as 3-state outputs. In addition to high performance, the device features latch-up protection, single event and upset protection. The P93U422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24pin LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges.
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
CS 2 CS 1
A3 A2 A1 A0 A5 A6 A7 G ND D0 O0 D1 NC
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
D0 D1 D2 D3 A0 A1 A2 A3 A4 A5 A6 A7
DATA INPUT CONTROL
WE OE
V CC A4 WE CS 1 OE CS 2 O3 D3 O2 D2 O1 NC
32 X 32 ARRAY
ROW DECODER
SENSE AMPS
O0 O1 O2 O3
A3 A2 A1 A0 A5 A6 A7 GND D0 O0 D1
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
V CC A4 WE CS 1 OE CS 2 O3 D3 O2 D2 O1
INDEX
A1 A2 A3 VCC A4 WE 3 4 5 6 7 8 9 10 D0 11 O0 12 13 14 2 1 24 23 22 21 20 19 18 17 16 15
A0 A5 NC A6 A7 GND
CS1 OE CS2 NC O3 D3
D1 O1
D 2 O2
COLUMN DECODER
SOIC (S4) TOP VIEW
DIP (P3-1, D3-1) TOP VIEW
LCC (L4) TOP VIEW
Means Quality, Service and Speed
1Q97
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P93U422
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value 0.5 to +7 0.5 to VCC +0.5 55 to +125 Unit V Symbol TBIAS TSTG V °C I OUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value 55 to +125 65 to +150 20 Unit °C °C mA
VTERM TA
RECOMMENDED OPERATING CONDITIONS
Grade(2) Commercial Military Ambient Temp 0°C to 70°C 55°C to 125°C Gnd 0V 0V Vcc 5.0V ±10% 5.0V ±10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF
Output Capacitance VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VOH VOL VIH VIL IIL IIH ISC ICC Parameter Output High Voltage Output Low Voltage Input High Level Input Low Level Input Low Current Input High Current Output Short Circuit Current (3) VIN = 0.40 V VCC = Max, VIN = 4.5V VCC = Max., VOUT = 0.0V All Inputs = GND VCC = Max. IIN = 10mA VOUT = 2.4V, VCC = Max. VOUT = 0.5V, VCC = Max. 50 TA = 125°C TA = 75°C TA = 0°C TA = 55°C VCL ICEX Input Clamp Voltage Output Leakage Current Test Conditions VCC = Min., VIN = VIH or VIL, IOH = 5.2 mA VCC = Min., VIN = VIH or VIL, IOL = 8.0 mA 2.1 0.8 300 40 70 70 70 80 90 1.5 50 V µA mA 2.4 0.45 P93U422 Min. Max. Unit V V V V µA µA mA
Power Supply Current
Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability
2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested.
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P93U422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/ reading operation of the memory. When chip select one (CS 1) and write enable (WE) are LOW and chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the "write recovery glitch." Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW.
TRUTH TABLE
Mode Standby Standby DOUT Disabled Read Write CS2 CS1 L X H H H X H L L L WE X X X H L OE X X H L X Output High Z High Z High Z DOUT High Z
Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state for the P93U422.
SWITCHING CHARACTERISTICS (5,6)
Over Operating Range (Commercial and Military)
Parameters tPLH(A)(7) tPLH(A)(7) tPZH (CS1, CS2)(8) tPZL (CS1, CS2)(8) tPZH (WE)(8) tPZL (WE)(8) tPZH (OE)(8) tPZL (OE)(8)
Description Delay from Address to Output (Address Access Time) (See Fig. 2) Delay from Chip Select to Active Output and Correct Data (See Fig. 2) Delay from Write Enable to Active Output and Correct Data (Write Recovery) (See Fig. 1) Delay from Output Enable to Active Output and Correct Data (See Fig. 2) Setup Time Address (Prior to Initiation of Write) (See Fig. 1) Hold Time Address (After Termination of Write) (See Fig. 1) Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1) Hold Time Data Input (After Termination of Write) (See Fig. 1) Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1) Hold Time Chip Select (After Termination of Write) (See Fig. 1) Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)
P93U422 Min. Max. 35 25 25 25 5 5 5 5 5 5 20 30 30 30
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tS(A) th(A) tS(DI) th(DI)
tS (CS1, CS2) th (CS1, CS2)
tpw(WE)
tPHZ (CS1, CS2) tPLZ (CS1, CS2)(8) tPHZ (WE)(8) tPLZ (WE)(8) tPHZ (OE)(8) tPLZ (OE)(8)
(8)
Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2) Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1) Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)
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