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Details, datasheet, quote on part number:GTLP16612AA
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Datasheet text preview:
CE 1D CI CLK
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
GTLP16612A
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
Product Description
Features
Bidirectional interface between GTLP and TTL logic levels Designed with Edge Rate Control Circuit to reduce output noise VREF pin provides external supply reference voltage for receiver threshold 5V tolerant inputs and outputs on A-Port Increased B-Port Drive, 50mA Bus-Hold data inputs on A-Port to eliminate the need for pull-up resistors for unused inputs Power up/down high impedance TTL compatible Driver and Control inputs A-Port Balanced Drive: 32mA/+32mA Flow-through architecture Open drain on GTLP to support wired-or connection Package: 56-pin 240 Mil Wide Plastic TSSOP (A)
Pericom Semiconductors GTLP series of logic circuits are produced using the Companys advanced 0.5 micron CMOS technology, achieving industry leading performance. The GTLP16612A 18-bit universal transceiver provides TTL to GTLP signal level translation. The device is designed to provide highspeed interface between cards operating at TTL logic levels and a back plane operating at GTLP logic levels. High-speed back plane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes signal settling times. Its function is similar to BTL or GTL but with modified driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V, and the receiver threshold is 1.0V.
Pin Configuration
OEAB LEAB A1 GND A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 CEAB CLKAB B1 GND B2 B3
VCCQ(5.0V)
Logic Block Diagram
OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA 1 56 55 2 28 30 29 27 CE 1D CI CLK 1 of 18 Channels
VCC(3.3V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14
B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA
56-Pin A,V
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
A1 3
GTLP
54
B1
A15 VCC(3.3V) A16 A17 GND A18 OEBA LEBA
V
1 of 18 Channels
1
PS8431
09/24/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
Pin Descriptions
Pin Name s OEAB OEBA CEAB CEBA LEAB LEBA CLKAB CLKBA VREF A1- A18 B1- B18 A- to- B Output Enable (Active LOW) B- to- A Output Enable (Active LOW) A- to- B Clock Enable (Active LOW) B- to- A Clock Enable (Active LOW) A- to- B Latch Enable (Transparent HIGH) B- to- A Latch Enable (Transparent HIGH) A- to- B Clock Pulse B- to- A Clock Pulse GTLP Input Reference Voltage A- to- B TTL Data Inputs or B- to- A 3- State Outputs B- to- A GTLP Data Inputs or A- to- B Open Drain Outputs De s cription
Functional Description
The PI74GTLP16612A combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode. The functional operation is described below:
Truth Table(1)
Inputs CEAB X L L X X L L H OEAB H L L L L L L L LEAB X L L H H L L L CLKAB X H L X X X A X X X L H L H X Output B Z B0(2) B0(3) L H L H B0(3) M ode Latched Storage of A Data Transparent Clocked Storage of A Data Clock Inhibit
Notes: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. 2. Output level before indicated steady-state input conditions were established, provided CLKAB was HIGH before LEAB went LOW. 3. Output level before indicated steady-state input conditions were established.
2
PS8431 09/24/99
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
Absolute Maximum Ratings(4)
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (TSTG) ..... 65°C to +150°C Supply Voltage (VCC, VCCQ) ......... 0.5V to +7.0V DC Input Voltage (VI) .. 0.5V to +7.0V DC Output Voltage (VO) Outputs 3-State ......... 0.5V to +7.0V Outputs Active(5) ........ 0.5V to VCC +0.5V DC Output Current into A-Port IOH /IOL ....... 64mA/+64mA DC Output Sink Current into B-Port in LOW State IOL .... 100mA DC Input Diode Current (IIK) VI VCC ......... +50mA ESD Performance ...... >2000V
Recommended Operating Condition(6)
Supply Voltage (VCC) VCC ...... 3.15V to 3.45V VCCQ .... 4.75V to 5.25V Bus Termination Voltage (VTT) .... 1.35V to 1.65V Input Voltage (VI) on A-Port and Control Pins ...... 0.0V to 5.5V HIGH Level Output Current (IOH) A-Port ........... 32mA LOW Level Output Current (IOL) A-Port ........... +32mA B-Port ............ +50mA Operating Temperature (TA) ...... 40°C to +85°C Notes: 4. The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The Recommended Operating Conditions table will define the conditions for actual device operation. 5. IO Absolute Maximum Rating must be observed 6. Unused inputs must be held HIGH or LOW.
3
PS8431
09/24/99
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