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Details, datasheet, quote on part number:PI29FCT520T/2520T
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Datasheet text preview:
FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520T/2520T PI29FCT521T
Fast CMOS Multilevel Pipeline Registers
Product Features:
· PI29FCT520T and PI29FCT521T are pinout and function compatible with IDT29FCT520/521, QS29FCT520/521 and AMD's Am29520/521 · Four 8-bit high-speed registers · Hold, Transfer, and load instructions · Dual two-level or single four-level pipeline operation · TTL input and output levels, reducing problematic "ground bounce" · High output drive IOL = 48 mA · Extremely low static power (1 mW, typ.) · Industrial operating temperature range: 40°C to +85°C · FCT (2xxxT) has a 25 series resistor. · Packages available: 24-pin 300 mil wide plastic DIP (P24) 24-pin 150 mil wide plastic QSOP (Q24) 24-pin 150 mil wide plastic TQSOP (R24) 24-pin 300 mil wide plastic SOIC (S24)
Product Description:
Pericom Semiconductor's PI29FCT series of logic circuits are pro-duced in the Company's advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI29FCT520T/2520T and PI29FCT521T are multilevel pipeline registers containing four 8-bit positive triggered registers which can be configured as a dual 2-level or a single 4-level pipeline. These products are designed for use as temporary storage or for storage delays in pipelined systems. The PI29FCT521T differs from the PI29FCT520T/2520T only in the way data is loaded into and between registers in the dual 2-level operation. When data is entered into the first level (I = 2 or I = 1) of the PI29FCT520T/2520T, the existing data in the first level is moved to the second level. In the PI29FCT521T, these instructions simply overwrite the data in the first level. Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0) causing the first level to change. In either part, I = 3 shift instruction puts the registers on hold. Device models available upon request.
ogic Block Diagram
Y0D7
D
8 1 2
C ,I1 0
UX
CEGISTER I R LK O ONTROL R CTAL EGISTER A1 R OCTAL EGISTER B1
R OCTAL EGISTER A2
R OCTAL EGISTER B2
L
0,S1
2
MUX
M
S
E 8
O
0Y7
1
PS2002B 12/10/96
1
12/18/96, 4:44 PM
FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
Product Pin Configuration
I0 I1 D0 D1 D2 D3 D4 D5 D6 D7 CLK GND
Product Pin Description
Pin Name Description Output Enable Input (Active LOW) for 3-State Output Port Clock Input. Enter data into registers on LOW-to-HIGH transistions Instruction Inputs Multiplexer Select. Inputs either register A1, A2, B1, or B2 data to be avaialbe at the output ports Register Inputs Register Outputs Ground Power
24 23 22 21 10 19 18 17 16 15 14 23
V CC S0 S1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 OE
2 1 3 4 5 4-PIN 6 P24 7 Q24 8 R24 9 S24 1 10 11 22
OE CLK I0,I1 S0,S1
Dx Yx GND VCC
Register Selection
S1 0 0 1 1 S0 0 1 0 1 Register B2 B1 A2 A1
PI29FCT520/T2520T Data Loading
DUAL 2-LEVEL SINGLE 4-LEVEL
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
I=2 NOTE: I = 3 FOR HOLD
I=1
I=0
PI29FCT521T Data Loading
DUAL 2-LEVEL SINGLE 4-LEVEL
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
I=2 NOTE: I = 3 FOR HOLD
I=1
I=0
2
PS2002B 12/10/96
2
12/18/96, 4:44 PM
FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........ 55°C to +125°C Ambient Temperature with Power Applied ......... -40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... 0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ....... 0.5V to +7.0V DC Input Voltage ....... 0.5V to +7.0V DC Output Current .. 120 mA Power Dissipation ........ 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 5V ± 5%)
Parameters V OH V OL VIH VIL IIH IIL IOZH IOZL VIK IO S IOFF VH Description Outp ut HIGH Voltage Outp ut LOW Voltage Inp ut HIGH Voltage Inp ut LOW Voltage Inp ut HIGH Current Inp ut LOW Current High Impedance Outp ut Current Clamp Diode Voltage Sh ort Circuit Current Power Down Disable Inp ut Hysteresis VCC = MIN., IIN = 18 mA VCC = MAX. , VOUT = GND VCC = GND, VOUT = 4.5V
(3)
Test Conditions(1) VCC = MIN., VIN = VIH VCC = MIN., VIN = VIH
OR
Min. 2.4
Typ(2) 3.0 0.3 0.3
Max.
Units V
VIL VIL
IOH = 15.0 mA IOL = 48 mA
0.5 0 0.5 0
V V V
OR
IOL = 12 mA (25 series) Guaran teed Logic HIGH Level Guaran teed Logic LOW Level VCC = MAX. VIN = VCC 2.0
0.8 1 1 1 1 0 .7 6 0 -- 1 20 -- 20 0 10 0 1 .2
V µA µA µA µA V mA µA mV
VCC = MAX. VCC = MAX.
VIN = GND VOUT = 2.7V VOUT = 0.5V
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4) CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ 6 8 Max. 10 12 Units pF pF
Notes: 1. For conditions show as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested.
3
PS2002B 12/10/96
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