|
Details, datasheet, quote on part number:PI6C2308A-4L
| |
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
Zero-Delay Clock Buffer
Product Features
· · · · · · · · · Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps External feedback pin allows outputs to be synchronized to the clock input 5V tolerant input* Operates at 3.3V VDD Test mode allows bypass of the PLL for system testing purposes (e.g., IBIS measurements) Clock frequency multipliers ½x to 4x dependent on option Space-saving Packages: 16-pin, 150-mil SOIC (W) 16-pin 173-mil TSSOP (L)
Functional Description
The PI6C2308 is a PLL-based, zero-delay buffer, with the ability to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of four outputs exist, and, depending on product option ordered, can supply either reference frequency, prescaled half frequency, or multiplied 2x or 4x input clock frequencies. The PI6C2308 family has a power-sparing feature: when input SEL2 is 0, the component will 3-state one or both banks of outputs depending on the state of input SEL1. A PLL bypass test mode also exists. This product line is available in high-drive and industrial environment versions. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2308 is characterized for both commercial and industrial operation.
* FB_IN and CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing
Notice: This device is subject to import restriction. Please refer
Block Diagram
FB_IN CLKIN ÷2 PLL OUTA1 OUTA2 OUTA3 OUTA4 ÷2 OUTB1 Option (-2, -3) PI6C2308 (-1, -1H, -2, -3, -4) OUTB2 OUTB3 OUTB4 FB_IN CLKIN PLL
to the Import Restriction Notice under the Ordering Information section.
Pin Configuration PI6C2308
MUX
Option (-3, -4) SEL1 SEL2 Decode Logic
CLKIN OUTA1 OUTA2 VDD GND OUTB1 OUTB2 SEL2
1 2 3 16-Pin 4 W, L 5 6 7 8
16 15 14 13 12 11 10 9
FB_IN OUTA4 OUTA3 VDD GND OUTB4 OUTB3 SEL1
MUX
OUTA1 OUTA2 OUTA3
SEL2 SEL1
Decode Logic ÷2 MUX
OUTA4
PI6C2308-6
OUTB1 OUTB2 OUTB3 OUTB4
1
PS8384D
12/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 Zero Delay Clock Buffer
Input Select Decoding for PI6C2308 (-1, -1H,-4)
SEL2 0 0 1 1 SEL1 0 1 0 1 OUTA [1-4] 3- State PLL CLK IN PLL OUTB [1-4] 3- State 3- State CLK IN PLL Output Source PLL PLL CLK IN PLL PLL O FF ON O FF ON
Input Select Decoding for PI6C2308 (-2,-3)
SEL2 0 0 1 1 SEL1 0 1 0 1 OUTA [1-4] 3- State PLL CLK IN PLL OUTB [1-4] 3- State 3- State CLK IN/2 PLL Output Source PLL PLL CLK IN PLL PLL O FF ON O FF ON
Input Select Decoding for PI6C2308-6
SEL2 0 0 1 1 SEL1 0 1 0 1 OUTA [1-4] 3- State CLK IN PLL PLL OUTB [1-4] 3- State CLK IN/2 PLL PLL/2 Output Source PLL CLK IN PLL PLL PLL O FF O FF ON ON
PI6C2308 Configurations
D e vice PI6C2308- 1 PI6C2308- 1H PI6C2308- 2 PI6C2308- 2 PI6C2308- 3 PI6C2308- 3 PI6C2308- 4 PI6C2308- 6 PI6C2308- 6 Fe e dback From O UTA or O UTB O UTA or O UTB O UTA O UTB O UTA O UTB O UTA or O UTB O UTA O UTB OUTA [1-4] Fre que ncy CLK IN CLK IN CLK IN 2X CLK IN 2X CLK IN 4X CLK IN 2X CLK IN CLK IN CLK IN or 2X CLK IN OUTB [1-4] Fre que ncy CLK IN CLK IN CLK IN/2 CLK IN CLK IN or CLK IN(1) 2X CLK IN 2XCLK IN CLK IN or CLK IN/2 CLK IN
Note: 1. Output phase is indeterminant (0° or 180° from CLKIN)
2
PS8384D
12/07/01
CLKIN - Input to OUTA/OUTB Delay (ps)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 Zero Delay Clock Buffer
Pin Description
Pin 1 2 , 3 , 14 , 15 4 , 13 5 , 12 6, 7, 10 ,11 8 9 16 C LK IN O UTA[1- 4] VDD GN D O UTB[1- 4] SEL2 SEL1 FB_IN Signal D e s cription Input clock reference frequency (weak pull- down) C lock output, Bank A (weak pull- down) 3.3V supply Ground C lock output, Bank B (weak pull- down) Select input, bit 2 (weak pull- up) Select input, bit 1 (weak pull- up) PLL feedback input
Zero Delay and Skew Control
800 600 400 200 0 -200 -400 -600 -800 -900
-25 -20
CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins
-15
-10
-5
0
5
10
15
20
25
PI6C2308-1H
PI6C2308-1,2,3,4,6
-1000 Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF)
The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally.
Maximum Ratings
Supply Voltage to Ground Potential ........... 0.5V to +7.0V DC Input Voltage (Except CLKIN) ...... 0.5V to VDD +0.5V DC Input Voltage CLKIN ............ 0.5 to 7V Storage Temperature ......... 65ºC to +150ºC Maximum Soldering Temperature (10 seconds) ......... 260ºC Junction Temperature ......... 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) .......... >2000V
3
PS8384D
12/07/01
|
|
