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Details, datasheet, quote on part number:PI74ALVCH16269A
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Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs
Product Features
· PI74ALVCH16269 is designed for low voltage operation · VCC = 2.3V to 3.6V · Hysteresis on all inputs · Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C · Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C · Bus Hold retains last active bus state during 3-State, eliminating the need for external pullup resistors · Industrial operation at 40°C to +85°C · Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor's PI74ALVCH series of logic circuits are produced using the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI7ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. It is particularly suitable as an interface between synchronous DRAM's and high-speed microprocessors. Data is stored on the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B-port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, and OEB2). To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Because OE is being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Logic Block Diagram
1
PS8379
04/16/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16269 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs
Product Pin Description
Pin Name OE CLK SEL CLKEN A,1B,2B GND VCC Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power
Truth Tables(1)
Inputs CLK OEA H H L L OEB H L H L A Z Z Active Active Outputs 1B,2B Z Active Z Active
Product Pin Configuration
OEA OEB1 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 NC SEL
A to B STORAGE (OEB = L)
INPUTS OUTPUTS CLK X A X L H L H 1B 1B0(2) L H X X 2B 2B0(2) X X L H
56 55 54 53 52 51 50 49 48 47
OEB2 CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
1 2 3 4 5 6 7 8 9 10
CLKENA1 CLKENA2 H L L X X H X X L L
11 46 12 56-PIN 45 13 A56 44 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
B to A STORAGE (OEA = L)
Inputs CLK X X SEL H L H H L L 1B X X L X X 2B X X X X L H Outputs A A0(2) A0(2) L H L H
V56
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Notes: 1. H = High Signal Level L = Low Signal Level X = Irrelevant Z = High Impedance = Transition, Low to High 2. Output level before indicated steady state input conditions established.
2
PS8379
04/16/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16269 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Note: Storage Temperature ...... 65°C to +150°C Stresses greater than those listed under MAXIMUM Supply Voltage Range, VCC ....... 0.5V to 4.6V RATINGS may cause permanent damage to the device. Input Voltage Range,VI: Except This is a stress rating only and functional operation of the I/O ports(1) ........ 0.5V to 4.6V device at these or any other conditions above those indicated in the operational sections of this specification I/O ports(1,2) ...... 0.5V to VCC + 0.5V (1,2) ...... 0.5V to V is not implied. Exposure to absolute maximum rating Output Voltage Range, VO CC + 0.5V conditions for extended periods may affect reliability. Input Clamp current, IIK (VI < 0) ........... 50mA Output Clamp current, IOK (VO < 0) ...... 50mA Continous Output Current, IO ........ ±50mA Continous Current through each VCC or GND .... ±100mA Maximum Power Dissipation: A package ....... 1W V package .... 1.4W Notes: 1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. This value is limited to 4.6V maximum.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ±10%)
Parame te rs VCC VIH(1) VIL(1) VIN(1) VOUT(1) IOH(1) De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 VCC = 2.3V HIGH- level Output Current VCC = 2.7V VCC = 3.0V VCC = 2.3V IOL(1) TA At/V LOW- level Output Current VCC = 2.7V VCC = 3.0V Operating Free- Air Temperature Input Transition Rise or Fall Rate - 40 Te s t Conditions M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC - 12 - 12 - 24 12 12 24 85 10 ºC ns/V mA V Typ. M ax. 3.6 Units
Input LOW Voltage Input Voltage Output Voltage
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3
PS8379
04/16/99
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