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Part: PI74FCT16501T
Category:
Logic
-> Bus Transceivers
-> CMOS/BiCMOS->FCT/FCT-T Family
Description: 18-Bit Registered Transceiver
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74FCT16501T datasheet File size : 313 kB
Request For quote: Find where to buy PI74FCT16501T
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16501/162501/162H501T PI74FCT16501T 18-BIT REGISTERED TRANSCEIVERS
PI74FCT162501T PI74FCT162H501T
Fast CMOS 18-Bit Registered Transceivers
Product Features
Common Features: · PI74FCT16501T, PI74FCT162501T, and PI74FCT162H501T are high-speed, low power devices with high current drive. · VCC = 5V ±10% · Hysteresis on all inputs · Packages available 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) PI74FCT16501T Features · High output drive: IOH = 32 mA; IOL = 64 mA · Power off disable outputs permit "live insertion" · Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C PI74FCT162501T Features · Balanced output drivers: ±24 mA · Reduced system switching noise · Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C PI74FCT162H501T Features · Bus Hold retains last active bus state during 3-state · Eliminates the need for external pull-up resistors
Product Description
Pericom Semiconductor's PI74FCT series of logic circuits are produced in the Company's advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16501T, PI74FCT162501T, and PI74FCT162H501T are 18-bit are registered bus transceivers designed with D-type latches and flip-flops to allow data flow in transparent, latched, and clocked modes. The Output Enable (OEAB and OEBA, Latch Enable (LEAB and LEBA) and Clock (CLKAB and CLKBA) inputs control the data flow in each direction. When LEAB is HIGH, the device operates in transparent mode for A-to-B data flow. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. The A bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB, if LEAB is LOW. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar using OEBA, LEBA and CLKBA. These high-speed, low power devices offer a flow-through organization for ease of board layout. The PI74FCT16501T output buffers are designed with a Power-Off disable allowing "live insertion" of boards when used as backplane drivers. The PI74FCT162501T has ±24 mA balanced output drivers. It is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. This eliminates the need for external terminating resistors for most interface applications. The PI74FCT162H501T has "Bus Hold" which retains the input's last state whenever the input goes to high-impedance preventing "floating" inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB C A1 D C B1 D
C D
C D
TO 17 OTHER CHANNELS
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PS2035A 03/11/96
Product Pin Description
Pin Name OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx GND VCC Note: Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs(1) B-to-A Data Inputs or A-to-B 3-State Outputs(1) Ground Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16501/162501/162H501T 18-BIT REGISTERED TRANSCEIVERS
Truth Table(1,4)
OEAB L H H H H H H Inputs LEAB CLKAB X X H X H X L L L L L H Ax X L H L H X X Outputs Bx Z L H L H B(2) B(3)
1. For the PI74FCT162H501T, these pins have "Bus Hold." All other pins are standard, outputs, or I/Os.
Product Pin Configuration
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A 10 A 11 GND A 12 A 13 A 14 VCC A 15 A 16 GND A 17 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 56-PIN 14 V56 15 A56 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND CLKAB B0 GND B1 B2 VCC B3 B4 B5 GND B6 B7 B8 B9 B 10 B 11 GND B 12 B 13 B 14 V CC B 15 B 16 GND B 17 CLKBA GND
Notes: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 4. H = High Voltage Level L = Low Voltage Level Z = High Impedance = LOW-to-HIGH Transition
2
PS2035A 03/11/96
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16501/162501/162H501T 18-BIT REGISTERED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........... 65°C to +150°C Ambient Temperature with Power Applied ... 40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) ..... 0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. 0.5V to +7.0V DC Input Voltage .......... 0.5V to +7.0V DC Output Current .... 120 mA Power Dissipation ......... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description VIH VIL IIH IIH IIH IIH IIL IIL IIL IIL IBHH IBHL I OZH ( 5 ) I O Z L( 5 ) VIK IOS IO VH Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Current Input HIGH Current Input HIGH Current Input LOW Current Input LOW Current Input LOW Current Input LOW Current Bus Hold Sustain Current High-Impedance Output Current (3-STATE OUTPUTS) Clamp Diode Voltage Short Circuit Current Output Drive Current Input Hysteresis Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input, VCC = Max. Standard I/O, VCC = Max. Bus Hold Input(4), VCC = Max. Bus Hold I/O(4), VCC = Max. Standard Input, VCC = Min. Standard I/O, VCC = Min. Bus Hold Input(4), VCC = Min. Bus Hold I/O(4), VCC = Min. Bus Hold Input(4), VCC = Min. VCC = Max. VCC = Max. VCC = Min., IIN = 18 mA VCC = Max.(3), VOUT = GND VCC = Max.(3), VOUT = 2.5V Min. 2.0 VIN = VCC VIN = VCC VIN = VCC VIN = VCC VIN = GND VIN = GND VIN = GND VIN = GND VIN = 2.0V VIN = 0.8V VOUT = 2.7V VOUT = 0.5V 0.8 1 1 ±100 ±100 1 1 ±100 ±100 50 +50 1 1 0.7 140 100 1.2 200 180 Typ(2) Max. Units V V µA µA µA µA µA µA µA µA µA µA µA V mA mA m V
80 50
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Pins with Bus Hold are identified in the pin description. 5. This specification does not apply to bi-directional functionalities with Bus Hold.
3
PS2035A 03/11/96
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