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Part: PI74FCT16511TA
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: 16-Bit Registered / Latched Transceiver
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74FCT16511TA datasheet File size : 313 kB
Request For quote: Find where to buy PI74FCT16511TA
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
PI74FCT16511T PI74FCT162511T
Product Features:
Common Features: · PI74FCT16511 and PI74FCT162511 are high-speed, low power devices with high current drive. · Vcc = 5V ±10% · Typical tsk(o) (Output Skew) < 250 ps, clocked mode · Extended range of 40°C to +85°C · Hysteresis on all inputs · Packages available: 56-pin 240 mil wide TSSOP (A) 56-pin 300 mil wide SSOP (V) PI74FCT16511T Features: · High output drive: IOH = 32 mA; IOL = 64 mA · Power off disable outputs permit "live insertion" · Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C PI74FCT162511T Features: · High output drive: IOL/IOH = 24 mA · Open drain parity error allows wire-OR · Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C · Balanced output drivers: ±24 mA · Series current limiting resistors
Fast CMOS 16-Bit Registered/Latched Transceiver With Parity
Product Description:
Pericom Semiconductor's PI74FCT series of logic circuits are produced in the Company's advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI74FCT16511T and PI74FCT162511T are high-speed, lowpower 16-bit registered/latched transceiver with parity which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. It has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. One error flag for each direction (A-to-B or B-to-A) exists to indicate an error for either byte in either direction. The parity error flags which are open drain outputs, can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. To disable the error flag during combinational transitions, a designer can disable the parity error flag by the OExx control pins. The operation in A-to-B direction is controlled by LEAB, CLKAB and OEAB control pins, and the operation in B-to-A direction is controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK is used to select the operation of A-to-B direction, while B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Independent operation can be achieved between the two directions by using the corresponding control lines except for the ODD/EVEN control.
Simplified Logic Block Diagram
LEAB CLKAB Data Parity, data 16 Parity GEN/CHK Byte Parity Generator/ Checker 2 Latch/ Register 18 B0-15 PB1,2 PERB (Open Drain) OEAB
A0-15 PA1,2 ODD/EVEN
LEBA CLKBA Parity, data 18 OEBA PERA (Open Drain) Latch/ Register Byte Parity Checking Parity, data 18
1
PS2080A 01/15/95
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Logic Block Diagram
ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB A0-A7 C D C C D D OEBA P C O PA1 D I C C D D C A8-A15 D C C D D C D B8-B15 P D C PB1 C D B0-B7
P C O PA2 D I C C D D C GEN/CHK D C PERA (Open Drain) C D D P C D (Open Drain) PERB D C PB2
2
PS2080A 01/15/95
Product Pin Description
Pin Name
OEAB OEBA CLKAB CLKBA LEAB LEBA PERA PERB Ax Bx ODD/EVEN(1) GEN/CHK(1) PAx(2) PBx GND VCC
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16511/162511T 16-BIT REGISTERED/ LATCHED TRANSCEIVER WITH PARITY
Product Pin Configuration
OEAB LEAB PA1 GND A0 A1 VCC A2 A3 A4 A5 A6 A7 GND PERA A8 A9 A10 A11 A12 A13 VCC A14 A15 GND PA2 OEBA LEBA
Description
A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Clock Input B-to-A Clock Input A-to-B Latch Enable Input B-to-A Latch Enable Input Parity Error (Open Drain) on A Outputs Parity Error (Open Drain) on B Outputs A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or B-to-A 3-State Outputs Parity Mode Selection Input A-to-B Port Generate or Check Mode Input A-to-B Parity Input, B-to-A Parity Output B-to-A Parity Input, A-to-B Parity Output Ground Power
1 2 3 4 5 6 7 8 9 10 11 12 56-PIN V56 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A56
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GENCHK CLKAB PB1 GND B0 B1 VCC B2 B3 B4 B5 B6 B7 PERB GND B8 B9 B10 B11 B12 B13 VCC B14 B15 GND PB2 CLKBA ODD/EVEN
NOTES: 1. ODD/EVEN and GEN/CHK should be tied to VCC or GND with no resistor for optimum results. 2. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A-to-B direction, there is no need to add a pull-up resistor to guarantee state. The pin will still function properly as the parity output for the B-to-A direction.
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1) CIN CI/O CO Description Input Capacitance I/O Capacitance Open Drain Capacitance Test Conditions VIN = 0V VOUT = 0V VOUT = 0V Typ 4.5 5.5 4.5 Max. 6.0 8.0 6.0 Units pF pF pF
Note: 1. This parameter is determined by device characterization but is not production tested.
3
PS2080A 01/15/95
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