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Part: PI74VCX16374A
Category:
Logic
-> Flip-Flops
-> CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage
Description: 16-Bit D-type Flip-flop W/3-State
Company: Pericom Semiconductor Corporation
Datasheet: Download PI74VCX16374A datasheet File size : 31 kB
Request For quote: Find where to buy PI74VCX16374A
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74VCX16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
Product Features
· The PI74VCX Family is designed for low voltage operation, VDD = 1.8V to 3.6V · 3.6V I/O Tolerant Inputs and Outputs · Supports Live Insertion · Balanced Drive, ±24mA · Uses patented Noise Reduction Circuitry · Typical VOLP (Output Ground Bounce) < 0.6V at VDD = 2.5V, TA = 25ºC · Typical VOHV (Output VOH Undershoot) < -0.6V at VDD = 2.5V, TA = 25ºC · Power-Off high impedance inputs and outputs · Industrial operation at 40°C to +85°C · Packages available: 48-pin 240 mil. wide plastic TSSOP (A) 48-pin 300 mil. wide plastic SSOP (V)
Product Description
Pericom Semiconductor's PI74VCX series of logic circuits are produced in the Company's advanced 0.35 micron CMOS technology, achieving industry leading speed. The PI74VCX16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit Flip-Flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the date (D) inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. The PI74VCX family is I/O Tolerant, allowing it to operate in mixed 1.8V/3.6V systems.
>C1
2
Logic Block Diagram
1OE
1
1CLK
48
1Q1
1D1
47
1D
To Seven Other Channels
24
2OE 2CLK
25
>C1
13
2Q1
2D1
36
1D
To Seven Other Channels
1
PS8327
09/14/98
Product Pin Description
Pin Name OE CLK Dx Qx GND VCC Description Output Enable Input (Active LOW) Clock Input Data Inputs 3-State Outputs Ground Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74VCX16374 16-Bit D-Type Flip-Flop with 3-State Outputs
Truth Table(1)
Inputs OE L L L H CLK H or L X D H L X X Outputs Q H L Q0 Z
Product Pin Configuration
Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance
48 47 46 45
1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK
48-PIN A48 V48
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2
PS8327
09/14/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74VCX16374 16-Bit D-Type Flip-Flop with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range, VDD ...... 0.5V to 4.6V Input Voltage Range, VI ......... -0.5V to 4.6V Output Voltage Range, VO (3-Stated) .. -0.5V to 4.6V Output Voltage Range, VO(1) (Active) ... 0.5V to VDD + 0.5V DC Input Diode Current (IIK) VI VDD ........... -50mA DC Output Source/Sink Current (IOH/IOL) .... ±50mA DC VDD or GND Current per Supply Pin (ICC or GND) .... ±100mA Storage Temperature Range, TSTG .... 65°C to150°C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f o r extended periods may affect reliability.
Recommended Operating Conditions(2)
Parame te rs VDD VIH VIL VI VO De s cription Supply voltage High- level input voltage Low- level input voltage Input voltage Output voltage Active State Off State VDD = 3.0V to 3.6V VDD = 2.3V to 2.7V VDD = 1.8V 0 -40 Conditions Operating Data Retention Only VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V - 0.3 0 0 M in. 1.8 1.2 2.0 0.8 3.6 VDD 3.6 ±24 ±18 ±6 10 85 mA ns/V C V M ax. 3.6 3.6 Units
Output current in IOH/IOL Dt/Dv TA
Input transistion rise or fall rate(3) Operating free- air temperature
Notes: 1. Absolute maximum of IO must be observed. 2. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8327
09/14/98
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