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Part: PI90SD1636AFD
Category:
Communication
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-> SerDes Transeivers
Description: Serdes Gigabit Ethernet Transceiver
Company: Pericom Semiconductor Corporation
Datasheet: Download PI90SD1636AFD datasheet File size : 856 kB
Request For quote: Find where to buy PI90SD1636AFD
Datasheet text preview:
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Features
· IEEE 802.3z Gigabit Ethernet Compliant · Supports 1.25 Gbps Using NRZ Coding over uncompensated twin coax cable · Fully integrated CMOS IC · Low Power Consumption · ESD rating >2000V (Human Body Model) or > 200V (Machine Model) · 5-Volt Input Tolerance · Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A and Vitesse VSC7123 transceivers (see Appendix A) · Available in both 10mm x10mm and 14mm x14mm 64-pin LQFP packages
Description
The PI90SD1636A is a single chip, Gigabit Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified by the IEEE 802.3z Gigabit Ethernet standard. These functions include parallel-to-serial and serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization. In addition, an internal loopback function is provided for system debugging. The PI90SD1636A is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports both 1000BASE-LX and 1000BASE-SX fiber-optic media, and 1000BASECX copper media. The transmitter section of the PI90SD1636A accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE SX fiber optic medium. The receiver section of the PI90SD1636A accepts a serial PECLcompatible data stream at a 1.25 Gbps rate, recovers the original 10bit wide parallel data format, and retimes the data. A Phase Lock Loop (PLL) locks on to the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by continually frequency locking on to the 125 MHz reference clock, and by phase locking on to the incoming data stream. The serial data is converted back to parallel data format. The `comma' character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form.
1
PS8641
12/05/02
EN_CDET COM_DET
FRAME ENABLE
10
Shift Registers
INPUT SELECTOR
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90SD1636A SERDES Gigabit Ethernet Transceiver
Functional Block Diagram
EWRAP
TX
10
Input Data Latch
10
Shift Registers
DOUT+ DOUT-
TX_CLK
TX PLL Clock Generator
62.5 MHz RX_CLK RX_CLK 62.5 MHz ÷2
125 MHz
10
RX
Output Latch
RX PLL Clock Recovery
10
DIN+ DIN-
2
PS8641
12/05/02
GND_RX_ESD
VCC_RX_ESD
GND_RXA
VCC_RX_ESD
GND_TX_HS
VCC_TX_ECL
VCC_TX_HS
GND_RXF
VCC_RXA
VCC_RXA
DOUT+
DOUT-
DIN+
DIN-
VCC_RXF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND_ESD TX TX TX VCC_ESD TX TX TX TX VCC_ESD TX TX TX GND_ESD GND_TXA NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC COM_DET GND_RXT RX RX RX VCC_RXT RX RX RX RX VCC_RXT RX RX RX GND_RXT
GND_RXD
GND_TXD
VCC_RXD
VCC_TXD
EWRAP
NC
RX_CLK
RX_CLK
VCC_RXD
EN_CDET
Table 1. I/O Type Definitions
Type TTL_IN TTL_OUT HS_IN HS_OUT P De finition TTL Input TTL Output High- Speed Input High- Speed Output Power and Ground
VCC_TXA
SIG_DET
GND_RX
VCC_RX
TX_CLK
NC
NC
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90SD1636A SERDES Gigabit Ethernet Transceiver
Pin Configuration (Top View)
3
PS8641
12/05/02
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