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Part: 4LVC652PWDH
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal Transceiver/register With Dual Enable 3-state
Company: Philips Semiconductors
Datasheet: Download 4LVC652PWDH datasheet File size : 67 kB
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INTEGRATED CIRCUITS
74LVC652 Octal transceiver/register with dual enable (3-State)
Product specification Supercedes data of 1993 Dec 01 IC24 Data Handbook 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transceiver/register with dual enable (3-State)
74LVC652
*FEATURES
· Wide supply voltage range of 1.2V to 3.6V · In accordance with JEDEC standard no. 8-1A · CMOS low power consumption · Direct interface with TTL levels · 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC652 is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC652 consist of 8 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the `A' or `B' or both buses, will be stored in the internal registers, at the appropriate clock inputs (CPAB or CPBA) regardless of the select inputs (SAB and SBA) or output enable (OEAB and OEBA) control inputs. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the OEn inputs this operating mode permits. The output enable inputs OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER tPHL/tPLH fmax CI CP D Propagation delay An to Bn; Bn to An Maximum clock frequency Input capacitance Power dissipation capacitance per latch Notes 1, 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 5.0 150 5.0 45 UNIT ns MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC652 D 74LVC652 DB 74LVC652 PW NORTH AMERICA 74LVC652 D 74LVC652 DB 4LVC652PW DH PKG. DWG. # SOT137-1 SOT340-1 SOT355-1
1998 Jul 29
2
853-2104 19803
Philips Semiconductors
Product specification
Octal transceiver/register with dual enable (3-State)
74LVC652
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER 1 SYMBOL CPAB SAB OEAB A0 to A7 GND B0 to B7 OEBA SBA CPBA VCC FUNCTION `A' to `B' clock input (LOW-to-HIGH, edge-triggered) Select `A' to `B' source input Output enable B to A input (active LOW) `A' data inputs/outputs Ground (0V) `B' data inputs/outputs Output enable A to B input Select `B' to `A' source input `B' to `A' clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
CP AB S AB OE AB A0 A1 A2 A3 A4 A5
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
V CC CP BA S BA OE BA B0 B1 B2 B3 B4 B5 B6 B7
2 3 4, 5, 6, 7, 8, 9, 10, 11 12 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 24
A 6 10 A7 GND 11 12
SV00767
FUNCTION TABLE
INPUTS OEAB L L X H L L L L H H H * OEBA H H H H X L L L H H L CPAB H or L H or L X X X H or L H or L CPBA H or L H or L X H or L X X H or L SAB X X X L X X X X L H H SBA X X X X X L L H X X H DATA I/O * A0 to A7 input input input un * output output input output B0 to B7 input un * output input input input output output FUNCTION isolation store A and B data store A, hold B, store A in both registers hold A, store B, store B in both registers real-time B data to A bus stored B data to A bus real-time A data to B bus stored A data to B bus stored A data to B bus and stored B data to A bus
un H L X
The data output functions may be enabled or disabled by various signals at the OEAB and OEBA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. = unspecified = HIGH voltage level = LOW voltage level = Don't care = LOWtoHIGH level transition
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal transceiver/register with dual enable (3-State)
74LVC652
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
21 OE BA
4 CP BA S BA B0 B1 B2 B3 B4 B5 B6 23 22 20 19 18 17 16 15 14 13 10 11 7 8 9
A A A A A A A A
0 1 2 3 4 5 6 7
B B B B B B B B
0 1 2 3 4 5 6 7
20 19 18 17 16 15 14 13
1 2 4 5 6 7 8 9 10 11
CP AB S AB A0 A1 A2 A3 A4 A5 A6 A7
5 6
OE AB 3
B7
21 3
OE OE S S
BA AB
SV00768
2
AB BA AB BA
LOGIC SYMBOL (IEEE/IEC)
23 C4 1 C5 22 G6 2 G7 21 3 3EN1 3EN2
22 1 23
CP CP
SV00770
4 1
w1 6 6 5D 1 7 7
4D 1 w1 2
20
5
19
6
18
7
17
8
16
9
15
10
14
11
13
SV00769
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal transceiver/register with dual enable (3-State)
74LVC652
LOGIC DIAGRAM
OE BA OE AB S BA CP BA S AB CP AB
V CC S D1 D
Y An
MUX D2 Q
FF n CP
V CC S D1 Y MUX D Q D2 Bn
FF n CP 8 identical channels
SV00771
1998 Jul 29
5
Others parts begin by 4l
4L-1
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