|
Details, datasheet, quote on part number:74ABT16501A
| |
| Part: | 74ABT16501A |
| Category: | Logic => Transceivers |
| Description: | 74ABT16501A; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56), SOT371-1 (SSOP56) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74ABT16501A datasheet File size : 107 kB |
| Request For quote: | Find where to buy 74ABT16501A
|
| |
Datasheet text preview:
INTEGRATED CIRCUITS
74ABT16501A 18-bit universal bus transceiver (3-State)
Product data Replaces 74ABT16501A/74ABTH16501A dated 1998 Feb 27 2002 Apr 03
Philips Semiconductors
Philips Semiconductors
Product data
18-bit universal bus transceiver (3-State)
74ABT16501A
FEATURES
· 18-bit bidirectional bus interface · 3-State buffers · Output capability: +64 mA/32 mA · TTL input and output switching levels · Live insertion/extraction permitted · Power-up reset · Power-up 3-State · Positive edge-triggered clock inputs · Latch-up protection exceeds 500mA per JEDEC Std 17 · ESD protection exceeds 2000 V per MIL STD 883 Method 3015 · Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, and latched modes. and 200 V per Machine Model
DESCRIPTION
The 74ABT16501A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is Active-HIGH, and OEBA is Active-LOW).
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ ICCL PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) I/O pin capacitance Quiescent supply current supply current CONDITIONS Tamb = 25 °C; GND = 0 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC Outputs disabled; VI/O = 0 V or VCC Outputs disabled; VCC = 5.5 V Outputs LOW; VCC = 5.5 V TYPICAL 2.2 1.8 3 7 500 9 UNIT ns pF pF µA mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE 40 °C to +85 °C 40 °C to +85 °C ORDER CODE 74ABT16501ADL 74ABT16501ADGG DWG NUMBER SOT371-1 SOT364-1
2002 Apr 03
2
853-1788 27958
Philips Semiconductors
Product data
18-bit universal bus transceiver (3-State)
74ABT16501A
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CPAB B0 GND B1 B2 VCC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VCC B15 B16 GND B17 CPBA GND
LOGIC SYMBOL
30 28 27 55 2 1
OEBA
OEAB
CPBA
LEBA
LEAB
CPAB
54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
SA00127
LOGIC SYMBOL (IEEE/IEC)
OEAB CPAB LEAB
1 55 2
EN1 2C3 C3 G2
OEBA CPBA LEBA
27 30 28
EN4 5C6 C6 G5
SA00128
A0
3
3D 4
1 1
1 6D
54
B0
PIN DESCRIPTION
PIN NUMBER 1 27 2, 28 55,30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL OEAB OEBA LEAB/LEBA CPAB/ CPBA A0-A17 NAME AND FUNCTION A-to-B Output enable input B-to-A Output enable input (Active-LOW) A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs (A side)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
B0-B17
Data inputs/outputs (B side) Ground (0 V) Positive supply voltage
A12 A13 A14
GND VCC
A15 A16 A17
SA00129
2002 Apr 03
3
Philips Semiconductors
Product data
18-bit universal bus transceiver (3-State)
74ABT16501A
FUNCTION TABLE
INPUTS OEAB L L L L L L H H H H H H H H LEAB H L L L H H L L L L CPAB X X X H or L X X X X H or L H or L An X h I X h I H L h I h I X X X H L NC H L H L H L H L H L Internal Registers Registers OUTPUTS OPERATING MODE MODE Bn Z Z Disabled, Latch data Latch data Z Z Z Disabled, Clock data Clock data Z H Transparent L H Latch data & display data dis L H Clock data & display data dis L H Hold data & display data dis L NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock transition NC = No Change X = Don't care Z = High Impedance "off" state = HIGH-to-LOW Enable or Clock transition = LOW-to-HIGH Clock transition Disabled, Hold data Disabled
2002 Apr 03
4
Philips Semiconductors
Product data
18-bit universal bus transceiver (3-State)
74ABT16501A
LOGIC DIAGRAM
OEAB
1
CLKAB 55
LEAB 2
LEBA
28
CLKBA 30
OEBA 27
A1
3
ID C1 CLK ID C1 CLK
54 B1
To 17 other channels
SW00235
2002 Apr 03
5
|
|
