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Details, datasheet, quote on part number:74ABT373AD
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| Part: | 74ABT373AD |
| Category: | Logic => Latches |
| Description: | 74ABT373A; Octal Transparent Latch (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20), SOT360-1 (TSSOP20) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74ABT373AD datasheet File size : 62 kB |
| Request For quote: | Find where to buy 74ABT373AD
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Datasheet text preview:
INTEGRATED CIRCUITS
74ABT373A Octal transparent latch (3-State)
Product specification IC23 Data Handbook 1995 Feb 17
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transparent latch (3-State)
74ABT373A
FEATURES
· 8-bit transparent latch · 3-State output buffers · Output capability: +64mA/32mA · Latch-up protection exceeds 500mA per JEDEC Std 17 · ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT373A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT373A device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
· Power-up 3-State · Power-up reset · Live insertion/extraction permitted
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.2 3.6 4 7 100 UNIT ns pF pF µA
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIP 20-Pin plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74ABT373A N 74ABT373A D 74ABT373A DB 74ABT373A PW NORTH AMERICA 74ABT373A N 74ABT373A D 74ABTD373A B 7ABT373APW DH DWG NUMBER SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER 1 SYMBOL OE D0-D7 Q0-Q7 E GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Enable input (active-High) Ground (0V) Positive supply voltage
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
V CC Q7 D7 D6 Q6 Q5 D5 D4 Q4 E
3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 11 10 20
GND 10
SA00059
1995 Feb 17
2
853-1454 14852
Philips Semiconductors
Product specification
Octal transparent latch (3-State)
74ABT373A
LOGIC SYMBOL
3 4 7 8 13 14 17 18
LOGIC SYMBOL (IEEE/IEC)
1 11
EN C1
D0 D1 D2 D3 D4 D5 D6 D7 11 1 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 13 2 5 6 9 12 15 16 19 14 17 3 4 7
1D
2 5 6 9 12 15 16 19
SA00060
18
FUNCTION TABLE
INPUTS OE L L L L L E H H L Dn L H l h X INTERNAL REGISTER L H L H NC OUTPUTS Q0 Q7 L H L H NC OPERATING MODE Enable and read register Latch and read register Hold
SA00061
H L X NC Z Disable outputs H H Dn Dn Z H = High voltage level h = High voltage level one set-up time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low E transition NC = No change X = Don't care Z = High impedance "off" state = High-to-Low E transition
LOGIC DIAGRAM
D0 3 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
11 E
1 OE 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
SA00062
1995 Feb 17
3
Philips Semiconductors
Product specification
Octal transparent latch (3-State)
74ABT373A
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING 0.5 to +7.0 18 1.2 to +7.0 50 0.5 to +5.5 128 65 to 150 UNIT V mA V mA V mA °C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 40 PARAMETER Min 4.5 0 2.0 0.8 32 64 5 +85 Max 5.5 VCC V V V V mA mA ns/V °C UNIT
1995 Feb 17
4
Philips Semiconductors
Product specification
Octal transparent latch (3-State)
74ABT373A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Min VIK Input clamp voltage VCC = 4.5V; IIK = 18mA VCC = 4.5V; IOH = 3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = 3mA; VI = VIL or VIH VCC = 4.5V; IOH = 32mA; VI = VIL or VIH VOL VRST II IOFF IPU/IPD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent su ly current supply Low-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.0V; VO = 0.5V; VOE = Don't Care V1 = GND or VCC VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 50 2.5 3.0 2.0 Typ 0.9 2.9 3.4 2.4 0.3 0.13 ±0.01 ±5.0 ±5.0 0.1 0.1 5.0 100 100 24 100 0.5 0.55 0.55 ±1.0 ±100 ±50 50 50 50 180 250 30 250 1.5 50 Max 1.2 2.5 3.0 2.0 0.55 0.55 ±1.0 ±100 ±50 50 50 50 180 250 30 250 1.5 Tamb = 40°C to +85°C Min Max 1.2 V V V V V V µA µA µA µA µA µA mA µA mA µA mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.4 1.4 1.4 1.9 1.2 2.1 1.3 1.2 Tamb = +25oC VCC = +5.0V Typ 3.2 3.6 3.2 3.7 3.1 4.2 3.4 3.0 Max 4.2 4.7 4.2 4.8 4.2 5.2 4.6 4.1 Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min 1.4 1.4 1.4 1.9 1.2 2.1 1.3 1.2 Max 4.7 5.1 4.8 5.1 5.1 5.7 5.1 4.3 ns ns ns ns UNIT
1995 Feb 17
5
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