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Part: 74ABT657
Category:
Logic
-> Parity Generators/Checkers
Description: 74ABT657; Octal Transceiver With Parity Generator/checker (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24), SOT340-1 (SSOP24), SOT355-1 (TSSOP24)
Company: Philips Semiconductors
Datasheet: Download 74ABT657 datasheet File size : 294 kB
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INTEGRATED CIRCUITS
74ABT657 Octal transceiver with parity generator/checker (3-State)
Product specification IC23 Data Handbook 1995 Dec 11
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT657
FEATURES
· Combinational functions in one package · Low static and dynamic power dissipation with high speed and · Output capability: +64mA/32mA · Power-up 3-State · Latch-up protection exceeds 500mA per Jedec Std 17 · ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model high output drive
DESCRIPTION
The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-State outputs and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 64mA. The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active-High) enables data from A ports to B ports; Receive (active-Low) enables data from B ports to A ports.
The Output Enable (OE) input disables both the A and B ports by placing them in a high impedance condition when the OE input is High. The parity select (ODD/EVEN) input gives the user the option of odd or even parity systems. The parity (PARITY) pin is an output from the generator/checker when transmitting from the port A to B (T/R = High) and an input when receiving from port B to A port (T/R = Low). When transmitting (T/R = High) the parity select (ODD/EVEN) input is set, then the A port data is polled to determine the number of High bits. The parity (PARITY) output then goes to the logic state determined by the parity select (ODD/EVEN) setting and by the number of High bits on port A. For example, if the parity select (ODD/EVEN) is set Low (even parity), and the number of High bits on port A is odd, then the parity (PARITY) output will be High, transmitting even parity. If the number of High bits on port A is even, then the parity (PARITY) output will be Low, keeping even parity. When in receive mode (T/R = Low) the B port is polled to determine the number of High bits. If parity select (ODD/EVEN) is Low (even parity) and the number of Highs on port B is: (1) odd and the parity (PARITY) input is High, then ERROR will be High, signifying no error. (2) even and the parity (PARITY) input is High, then ERROR will be asserted Low, indicating an error.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.3 4 7 500 UNIT ns pF pF nA
ORDERING INFORMATION
PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74ABT657 N 74ABT657 D 74ABT657 DB 74ABT657 PW NORTH AMERICA 74ABT657 N 74ABT657 D 74ABT657 DB 74ABT657PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
T/R 1 24 OE 23 B0 22 B1 21 B2 20 B3 19 GND TOP VIEW 18 GND 17 B4 16 B5 15 B6 14 B7 13 PARITY
PIN DESCRIPTION
SYMBOL 13 11 12 1 2, 3, 4, 5, 6, 8, 9, 10 23, 22, 21, 20, 17, 16, 15, 14 24 18, 19 7 PIN NUMBER PARITY ODD/EVEN ERROR T/R A0 - A7 B0 - B7 OE GND VCC NAME AND FUNCTION Parity output Parity select input Error output Transmit/receive input A port 3-State outputs B port 3-State outputs Output enable input (active-Low) Ground (0V) Positive supply voltage
A0 2 A1 3 A2 4 A3 5 A4 6 V CC 7 A5 8 A6 9 A7 10 ODD/EVEN 11 ERROR 12
SA00181
1995 Dec 11
2
8531615 16106
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT657
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1 0 1
2
3
4
5
6
8
9
10
24 11
M
20
0 2 K
B U S B TO A 1 B U S A TO B 2 HIGH Z
A0 A1 A2 A3 A4 A5 A6 A7 1 24 11 T/R OE ODD/EVEN ERROR 12 PARITY 13
G3[EVEN] G4[ODD]
B0 B1 B2 B3 B4 B5 B6 B7 2 23 22 21 20 17 16 15 14 3 4 5
= 1,3[EVEN] 1,4[ODD] 0,3[EVEN 0,4]ODD 2
13 12 23 22 21 20 17 16 15 14
0
SA00182
6 8 9 10
SA00194
FUNCTION TABLE
NUMBER OF HIGH INPUTS OE L L L L L L L L L L L L H INPUTS T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X INPUT/ OUTPUT PARITY H L H L H L L H H L H L Z ERROR Z Z H L L H Z Z L H H L Z OUTPUTS OUTPUTS MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive 3-State
0, 2, 4, 6, 8
1, 3, 5, 7
Don't care H L X Z = = = = High voltage level Low voltage level Don't care High impedance "off" state
1995 Dec 11
3
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT657
LOGIC DIAGRAM
T/R 1
OE A0
24 2 23 B0 22 B1 21 B2 20 B3 17 B4 16 B5 15 B6 14 B7
A1
3
A2
4
A3
5
A4
6
A5
8
A6
9
A7
10
ODD/EVEN
11
13 PARITY
12
ERROR
SA00215
1995 Dec 11
4
Philips Semiconductors
Product specification
Octal transceiver with parity generator/checker (3-State)
74ABT657
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING 0.5 to +7.0 18 1.2 to +7.0 50 0.5 to +5.5 128 65 to 150 UNIT V mA V mA V mA °C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 40 PARAMETER Min 4.5 0 2.0 0.8 32 64 5 +85 Max 5.5 VCC V V V V mA mA ns/V °C UNIT
1995 Dec 11
5
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