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Part: 74ABTH16841ADL
Category:
Logic
-> Latches
Description: 74ABT16841A; 74ABTH16841A; 20-bit Bus Interface Latch (3-State);; Package: SOT371-1 (SSOP56)
Company: Philips Semiconductors
Datasheet: Download 74ABTH16841ADL datasheet File size : 294 kB
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INTEGRATED CIRCUITS
74ABT16841A 74ABTH16841A 20-bit bus interface latch (3-State)
Product data Supersedes data of 1998 Feb 27 2002 Dec 17
Philips Semiconductors
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
FEATURES
· High speed parallel latches · Live insertion/extraction permitted · Extra data width for wide address/data paths or buses carrying · Power-up 3-State · 74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs parity
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. Data appears on the bus when the Output Enable (nOE) is LOW. When nOE is HIGH the output is in the high-impedance state. Two options are available, 74ABT16841A which does not have the bus-hold feature and 74ABTH16841A which incorporates the bus-hold feature.
· Power-up reset · Ideal where high speed, light loading, or increased fan-in are · Output capability: +64 mA / 32 mA · Latch-up protection exceeds 500 mA per Jedec Std 17 · ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model required with MOS microprocessors
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ ICCL PARAMETER Propagation delay nDx to nQx Input capacitance Output capacitance Quiescent supply current supply current CONDITIONS Tamb = 25 °C; GND = 0 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC VO = 0 V or VCC; 3-State Outputs disabled; VCC = 5.5 V Outputs LOW; VCC = 5.5 V TYPICAL 3.1 2.2 4 7 500 10 UNIT ns pF pF µA mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III TEMPERATURE RANGE 40 °C to +85 °C 40 °C to +85 °C 40 °C to +85 °C PART NUMBER 74ABT16841ADL 74ABT16841ADGG 74ABTH16841ADL DWG NUMBER SOT371-1 SOT364-1 SOT371-1
PIN DESCRIPTION
PIN NUMBER 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1, 28 56, 29 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1D0 1D9 2D0 2D9 1Q0 1Q9 2Q0 2Q9 1OE, 2OE 1LE, 2LE GND VCC Data inputs Data outputs Output enable inputs (active-LOW) Latch enable inputs (active rising edge) Ground (0 V) Positive supply voltage FUNCTION
2002 Dec 17
2
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 V CC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 V CC 2Q6 2Q7 GND 2Q8 2Q9 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1D0 1D1 GND 1D2 1D3 V CC 1D4 1D5
LOGIC SYMBOL (IEEE/IEC)
1OE 1LE 2OE 2LE 1D0 1D1 1D2 1D3 1D4 1D6 1D5 GND 1D7 1D8 1D9 2D0 2D1 2D2 GND 2D3 2D4 2D5 V CC 2D6 2D7 GND 2D8 2D9 2LE 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 1 56 28 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
SH00081
FUNCTION TABLE
INPUTS nOE nLE H H X nDx L H l h X OUTPUTS nQ0 nQ9 L H L H Z OPERATING MODE MODE
SA00076
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
L L L L H
Transparent Latched High impedance
1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1 1LE 1OE
1D7 1D8
1D9
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2 42
3 41
5 40
6 38
8 37
9 36
10 34
12 33
13 31
14 30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 28 2LE 2OE
2D7 2D8
2D9
L L X NC Hold H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = HIGH-to-LOW LE transition NC = No change X = Don't care Z = High impedance "off" state
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
2002 Dec 17
3
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
SH00024
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 V Output in Off or HIGH state Output in LOW state DC output current output current Output in HIGH state Storage temperature range 64 65 to 150 °C VI < 0 V CONDITIONS RATING 0.5 to +7.0 18 1.2 to +7.0 50 0.5 to +5.5 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage HIGH-level input voltage LOW-level Input voltage HIGH-level output current LOW-level output current Input transition rise or fall rate Operating free-air temperature range PARAMETER Min 4.5 0 2.0 0 40 Max 5.5 VCC 0.8 32 64 5 +85 V V V V mA mA ns/V °C UNIT
2002 Dec 17
4
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 °C Min VIK VOH VOL VRST II Input clamp voltage HIGH-level output voltage LOW-level output voltage Power-up output voltage3 Input leakage current leakage current 74ABT16841A Input leakage current leakage current 74ABTH16841A Bus Hold current inputs6 Hold current inputs 74ABTH16841A Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 Quiescent supply current Additional supply current per input pin2 VCC = 4.5 V; IIK = 18 mA VCC = 4.5 V; IOH = 3 mA; VI = VIL or VIH VCC = 5.0 V; IOH = 3 mA; VI = VIL or VIH VCC = 4.5 V; IOH = 32 mA; VI = VIL or VIH VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VCC = 5.5 V; IO = 1 mA; VI = GND or VCC VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; VI = VCC VCC = 5.5 V; VI = 0 V VCC = 4.5 V; VI = 0.8 V VCC = 4.5 V; VI = 2.0 V VCC = 5.5 V; VI = 0 to 5.5 V IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC VCC = 0.0 V; VO or VI 4.5 V VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; VOE = Don't care VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; Outputs High, VI = GND or VCC VCC = 5.5 V; Outputs Low, VI = GND or VCC VCC = 5.5 V; Outputs 3-State; VI = GND or VCC VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND 50 IHOLD Control pins Data pins5 ins 35 75 ±800 ±5.0 ±5.0 5.0 5.0 5.0 70 0.5 10 0.5 0.2 ±100 ±50 10 10 50 180 1 19 1 1 50 ±100 ±50 10 10 50 180 1 19 1 1 µA µA µA µA µA mA mA mA mA mA 2.5 3.0 2.0 Typ 0.9 2.9 3.4 2.4 0.42 0.13 ±0.01 ±0.01 0.01 2 0.55 0.55 ±1 ±1 1 3 35 75 µA Max 1.2 2.5 3.0 2.0 0.55 0.55 ±1.0 ±1 1 5 Tamb = 40 °C to +85 °C Min Max 1.2 V V V V V V µA µA µA µA UNIT
II
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 msec. From VCC = 2.1 V to VCC = 5 V ± 10% a transition time of up to 100 µsec is permitted. 5. Unused pins at VCC or GND. 6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nLE to nQx Output enable time to HIGH and LOW level Output disable time from HIGH and LOW level 2 1 4 5 4 5 1.1 1.5 1.5 1.0 1.2 1.2 1.8 1.5 Tamb = +25 °C VCC = +5.0 V TYP 3.1 2.2 2.5 2.1 2.4 2.2 3.0 2.5 MAX 4.1 3.1 3.3 2.8 3.2 2.9 4.0 3.2 Tamb = 40 °C to +85 °C VCC = +5.0 V ±0.5 V MIN 1.1 1.5 1.5 1.0 1.2 1.2 1.8 1.5 MAX 4.9 3.6 3.7 3.1 4.0 3.6 4.9 3.7 ns ns ns ns UNIT
2002 Dec 17
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