Details, datasheet, quote on part number: 74ABTH16899
Part74ABTH16899
CategoryLogic => Parity Generators/Checkers
Description74ABT16899; 74ABTH16899; 18-bit Latched Transceiver With 16-bit Parity Generator/checker (3-State);; Package: SOT364-1 (TSSOP56), SOT371-1 (SSOP56)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74ABTH16899 datasheet
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Features, Applications

Product specification Supersedes data of 1997 Mar 28 IC23 Data Handbook 1998 Feb 25
FEATURES

Symmetrical (A and B bus functions are identical) Selectable generate parity or "feed-through" parity for A-to-B and

Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.

Independent transparent latches for A-to-B and B-to-A directions Selectable ODD/EVEN parity Continuously checks parity of both A bus and B bus latches as

The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of:

Open-collector ERR output Ability to simultaneously generate and check parity Can simultaneously read/latch A and B bus data Output capability: +64 mA/32mA Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015

Power up 3-State Power-up reset Live insertion/extraction permitted Bus-hold data inputs eliminate the need for external pull-up

DESCRIPTION

The to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

Transparent latch / 1 bus latched / both buses latched Feed-through parity / generate parity Check in bus parity / check out bus parity / check in and out bus

SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ ICCL Propagation delay to An Propagation delay An to ERRA Input capacitance Output capacitance Quiescent supply current PARAMETER CONDITIONS Tamb = 25C; GND = 50pF; VCC = 50pF; VCC 0V or VCC Outputs disabled; 0V or VCC Outputs disabled; VCC =5.5V Output Low; VCC = 5.5V TYPICAL UNIT A mA

PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85C OUTSIDE NORTH AMERICA DL 74ABT16899 DGG DL 74ABTH16899 DGG NORTH AMERICA DL BT16899 DGG DL BH16899 DGG DWG NUMBER SOT371-1 SOT364-1

SYMBOL 1BPAR 2BPAR ODD/EVEN OEA, OEB SEL LEA, LEB 2ERRA, 2ERRB GND VCC PIN NUMBER NAME AND FUNCTION Latched A bus 3-State inputs/outputs Latched B bus 3-State inputs/outputs A bus parity 3-State input B bus parity 3-State input Parity select input (Low for EVEN parity) Output enable inputs (gate to A) Mode select input (Low for generate) Latch enable inputs (transparent High) Error signal outputs (active-Low) Ground (0V) Positive supply voltage


 

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