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Part: 74ABTH16899DL
Category:
Logic
-> Parity Generators/Checkers
Description: 74ABT16899; 74ABTH16899; 18-bit Latched Transceiver With 16-bit Parity Generator/checker (3-State);; Package: SOT364-1 (TSSOP56), SOT371-1 (SSOP56)
Company: Philips Semiconductors
Datasheet: Download 74ABTH16899DL datasheet File size : 294 kB
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INTEGRATED CIRCUITS
74ABT16899 74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State)
Product specification Supersedes data of 1997 Mar 28 IC23 Data Handbook 1998 Feb 25
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit parity generator/checker (3-State)
74ABT16899 74ABTH16899
FEATURES
ˇ Symmetrical (A and B bus functions are identical) ˇ Selectable generate parity or "feed-through" parity for A-to-B and
B-to-A directions
Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
ˇ Independent transparent latches for A-to-B and B-to-A directions ˇ Selectable ODD/EVEN parity ˇ Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of:
ˇ Open-collector ERR output ˇ Ability to simultaneously generate and check parity ˇ Can simultaneously read/latch A and B bus data ˇ Output capability: +64 mA/32mA ˇ Latch-up protection exceeds 500mA per Jedec Std 17 ˇ ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
ˇ Power up 3-State ˇ Power-up reset ˇ Live insertion/extraction permitted ˇ Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.
ˇ Transparent latch / 1 bus latched / both buses latched ˇ Feed-through parity / generate parity ˇ Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL CIN CI/O ICCZ ICCL Propagation delay An to Bn or Bn to An Propagation delay An to ERRA Input capacitance Output capacitance Quiescent supply current supply current PARAMETER CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V Output Low; VCC = 5.5V TYPICAL 2.7 5.0 4 7 500 10.5 UNIT ns ns pF pF ľA mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74ABT16899 DL 74ABT16899 DGG 74ABTH16899 DL 74ABTH16899 DGG NORTH AMERICA BT16899 DL BT16899 DGG BH16899 DL BH16899 DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1
1998 Feb 25
2
853-1960 19018
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit parity generator/checker (3-State)
74ABT16899 74ABTH16899
PIN CONFIGURATION
ODD/EVEN OEA 1A0 GND 1A1 1A2 1A3 1A4 VCC 1A5 1A6 1A7 1APAR 1ERRA GND 2ERRA 2APAR 2A7 2A6 2A5 VCC 2A4 2A3 2A2 2A1 GND 2A0 LEB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SEL LEA 1B0 GND 1B1 1B2 1B3 1B4 VCC 1B5 1B6 1B7 1BPAR 1ERRB GND 2ERRB 2BPAR 2B7 2B6 2B5 VCC 2B4 2B3 2B2 2B1 GND 2B0 OEB
SH00082
PIN DESCRIPTION
SYMBOL 1A0 - 1A7 2A0 - 2A7 1B0 - 1B7 2B0 - 2B7 1APAR 2APAR 1BPAR 2BPAR ODD/EVEN OEA, OEB SEL LEA, LEB 1ERRA, 1ERRB 2ERRA, 2ERRB GND VCC PIN NUMBER 3, 5, 6, 7, 8, 10, 11, 12 27, 25, 24, 23, 22, 20, 19, 18 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 13, 17 44, 40 1 2, 29 56 55, 28 14, 43, 16, 41 4, 15, 26, 31, 42, 53 9, 21, 36, 48 NAME AND FUNCTION Latched A bus 3-State inputs/outputs Latched B bus 3-State inputs/outputs A bus parity 3-State input B bus parity 3-State input Parity select input (Low for EVEN parity) Output enable inputs (gate A to B, B to A) Mode select input (Low for generate) Latch enable inputs (transparent High) Error signal outputs (active-Low) Ground (0V) Positive supply voltage
1998 Feb 25
3
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit parity generator/checker (3-State)
74ABT16899 74ABTH16899
LOGIC SYMBOL
3 5 6 7 8 10 11 12 13 27 25 24 23 22 20 19 18 17
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR 55 28 56 1 2 29 LEA LEB SEL ODD/EVEN OEA OEB 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1BPAR 1ERRA 1ERRB 14 43 55 28 56 1 2 29
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR LEA LEB SEL ODD/EVEN OEA OEB 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR 2ERRA 2ERRB 16 41
54
52
51
50
49
47
46
45
44
30
32
33
34
35
37
38
39
40
SH00083
PARITY AND ERROR FUNCTION TABLE
INPUTS SEL H H H H L L L L H L t r * ODD/EVEN H H L L H H L L xPAR (A or B) H L H L H L H L of High Inputs Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd Even Odd xPAR (B or A) H H L L H H L L H L H L L H L H OUTPUTS ERRt H L L H L H H L H L L H L H H L ERRr* H L L H L H H L H H H H H H H H PARITY MODES Odd Mode Feed-through/check parity
Even Mode
Odd Mode Generate parity
Even Mode
= High voltage level = Low voltage level = Transmitif the data path is from AB then ERRt is ERRA = Receiveif the data path is from AB then ERRr is ERRB Blocked if latch is not transparent
1998 Feb 25
4
Philips Semiconductors
Product specification
18-bit latched transceiver with 16-bit parity generator/checker (3-State)
74ABT16899 74ABTH16899
BLOCK DIAGRAM
OE 9bit Transparent Latch OEB
9bit Output Buffer
LEA A0 A1 A2 A3 A4 A5 A6 A7 APAR
LE Parity Generator 1 mux 0 B0 B1 B2 B3 B4 B5 B6 B7 BPAR 9bit Transparent Latch 9bit Output Buffer
OEA
OE 1 mux 0 Parity Generator
LE
LEB
ERRA
SEL
ERRB
ODD/ EVEN
(1 of 2 parity blocks)
SH00084
FUNCTION TABLE
INPUTS OEB H H H H H H L L L L L L OEA H L L L L L H H H H H L SEL X L L L H H L L L H H X LEA X L H X X H H H L H H X LEB X H H L H H X H X L H X 3-State A bus and B bus (input A & B simultaneously) B A, transparent B latch, generate parity from B0 - B7, check B bus parity B A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity B A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity B A, transparent B latch, parity feed-through, check B bus parity B A, transparent A & B latch, parity feed-through, check A & B bus parity A B, transparent A latch, generate parity from A0 - A7, check A bus parity A B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity A B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity A B, transparent A latch, parity feed-through, check A bus parity A B, transparent A & B latch, parity feed-through, check A & B bus parity Output to A bus and B bus (NOT ALLOWED) OPERATING MODE
H = High voltage level L = Low voltage level X = Don't care
1998 Feb 25
5
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