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Details, datasheet, quote on part number:74ABTL3205BB
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Datasheet text preview:
INTEGRATED CIRCUITS
74ABTL3205 10-bit BTL transceiver with registers
Product specification 1995 Jun 16
Philips Semiconductors
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FEATURES
· 10-bit BTL transceiver · Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
DESCRIPTION
This transceiver is a 10 bit bidirectional transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading (<6pF) by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. To support live insertion, OEB is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. This transceiver function is intended to operate in a half-duplex mode. Low current in standby mode is obtained by powering down unused circuitry. Likewise, transmit circuitry is powered down when in receive mode and receive circuitry is powered down while in transmit mode.
· High drive 100mA BTL open collector drivers on B-port · Allows incident wave switching in heavily loaded backplane buses · Reduced BTL voltage swing produces less noise and reduces
power consumption
· Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
· Compatible with IEEE Futurebus+ or proprietary BTL backplanes · Controlled output ramp and multiple GND pins minimize ground
bounce
· Tight output skew (0.5nsec typical) · Glitch-free power up/down operation · Low ICC current · Supports live insertion · High density packaging · ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL Propagation delay An to Bn Propagation delay Bn to An Output capacitance (B0 - B8) only) Output current (B0 - B8) only) Standby ICC Supply current An to Bn Bn to An PARAMETER TYPICAL 3.3 3.7 3.6 3.5 6 100 1 7 18 mA UNIT ns ns pF mA
ORDERING INFORMATION
PACKAGES 52-PIN PQFP TEMPERATURE RANGE 40°C to +85°C OUTSIDE NORTH AMERICA 74ABTL3205 BB NORTH AMERICA 74ABTL3205 BB DWG NUMBER SOT379-1
1995 Jun 16
2
853-1802 15352
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
PIN CONFIGURATION
BUS GND TTL Gnd AClk1 AClkin Recmode OEA1 OEA2 BClk1 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 AFP A7 APAR IEA Transmode BUS GND BG VCC BG GND Power Up TTL Gnd VCC M/S B7 BiasV Mode
VCC
OEB
52 TTL Gnd A0 A1 TTL GND A2 A3 TTL GND AClk2 TTL GND A4 A5 TTL GND A6 1 2 3 4 5 6 7 8 9 10 11 12 13
51 50 49 48 47 46 45 44 43 42 41 40 BUS GND B0 B1 BUS GND B2 B3 BUS GND BClk2 BUS GND B4 B5 BUS GND B6
VCC
SA00138
PIN DESCRIPTION
SYMBOL OEA1 OEA2 OEB IEA M/S FUNCTION Output enable data receiver group 1 Output enable data receiver group 2 Output enable data transmitter Output enable clock and framepulse receiver Master/Slave select: L: Master, enable clock transmitter H: Slave, disable clock transmitter Low: High: Power Up Recmode Tranmode AClk1 AClkln Data through mode Registered data mode Low High High Input Input Input I/O I/O TTL TTL TTL TTL TTL ASSERTION Low Low Low Low I/O Input Input Input Input Input LOGIC TTL TTL TTL TTL TTL
Mode
Input
TTL
Power up mode, held low during power up to disable clock and data transmitters Enables receiver Enables transmitter Clock or data path IEA = H Input for busclock IEA = L Output for busclock data group 1 Clock or data path Alternate data path Alternate data path data group 2 Clock or data path data group 1 Clock or data path data group 2
A0..A3 AClk2 AFPIn APAR A4..A7 BClk1 B0..B3 BClk2 B4..B7
I/O I/O Output Input I/O I/O I/O I/O I/O
TTL TTL TTL TTL TTL BTL BTL BTL BTL
1995 Jun 16
3
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
LOGIC DIAGRAM
ACLKin I/O
ACLK1 I/O
BCLK1 I/O
ACLK2 I/O
AFP OUT
APAR IN
D C
Q
BCLK2 I/O
B0-B3 A0-A3 I/O I/O D C Q
B4-B7 A4-A7 I/O I/O D C IEA IN OEB IN M/S IN OEA1 IN OEA2 IN RECMODE IN MODE IN TRANMODE IN POWERUP IN Definition for the MUX: Q
Low
High
SA00139
1995 Jun 16
4
Philips Semiconductors
Product specification
10-bit BTL transceiver with registers
74ABTL3205
FUNCTION TABLE
INPUTS MODE An to Bn (REGISTERED) AN to Bn (THROUGH) B0-B3 to A0-A3 (THROUGH) B4-B7 to A4-A7 (THROUGH) ACLK1 to BCLK1 ACLK2 to BCLK2 BCLK1 to ACLK1 BCLK2 to ACLK2 APAR to BCLK2 BCLK2 to AFPIn BCLK1 to ACLKin An I h L H O O O O X X X X X X X X X X X X X X Bn O O O O L H L H X X X X X X X X X X X X X X ACLK in ° ° X X X X X X X X X X X X X X ° ° X X O O ACLK 1 X X X X X X X X L H X X O O X X X X X X X X ACLK 2 X X X X X X X X X X L H X X O O X X X X X X BCLK 1 X X X X X X X X O O X X L H X X X X X X L H BCLK 2 X X X X X X X X X X O O X X L H X X L H X X OEA1 H H H H L L X X H H X X L L X X X X X X H H OEA2 H H H H X X L L X X H H X X L L X X X X H H OEB L L L L H H H H X X H H X X X X L L X X L L APAR X X X X X X X X X X X X X X X X I h X X O O IEA H H X X X X X X X X X X X X X X X X L L L L M/S X X X X X X X X L L L L X X X X H H X X H H MODE H H L L X X X X X X L L X X X X H H X X H H REC MODE L L L L H H H H X X X X H H H H X X H H L L TRAN MODE H H H H L L L L H H H H L L L L H H L L H H POWER UP H H H H L L L L H H H H X X X X H H X X H H
OUTPUTS MODE An to Bn (REGISTERED) AN to Bn (THROUGH) B0-B3 to A0-A3 (THROUGH) B4-B7 to A4-A7 (THROUGH) ACLK1 to BCLK1 ACLK2 to BCLK2 BCLK1 to ACLK1 BCLK2 to ACLK2 APAR to BCLK2 BCLK2 to AFPIn BCLK1 to ACLKin An Input Input Input Input H L H L X X X X X X X X X X X X X X Bn H* L H* L Input Input Input Input X X X X X X X X X X X X X X ACLK in X X X X Input Input Input Input X X X X X X X X Input Input X X H L ACLK1 X X X X X X X X Input Input X X H L X X X X X X X X ACLK2 X X X X X X X X X X Input Input X X H L X X X X X X BCLK1 X X X X X X X X H* L X X Input Input X X X X X X Input Input BCLK2 X X X X X X X X X X H* L X X Input Input H* L Input Input X X AF Pin X X X X X X X X X X X X X X X X X X H* L X X °
NOTES: H = High voltage level L = Low voltage level h = High voltage level one set-up time prior to Low to High ACLKin transition l = Low voltage level one set-up time prior to Low to High ACLKin transition = Low to High transition Z = High impedance (off) state H* = Goes to level of pull-up voltage X = Don't care O = Output
1995 Jun 16
5
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