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Details, datasheet, quote on part number:74AHC02PW
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| Part: | 74AHC02PW |
| Category: | Logic => Gates => NOR Gates |
| Description: | 74AHC02; 74AHCT02; Quad 2-input NOR GATE;; Package: SOT108-1 (SO14), SOT402-1 (TSSOP14) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74AHC02PW datasheet File size : 84 kB |
| Request For quote: | Find where to buy 74AHC02PW
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74AHC02; 74AHCT02 Quad 2-input NOR gate
Product specification Supersedes data of 1998 Dec 18 File under Integrated Circuits, IC06 1999 Sep 23
Philips Semiconductors
Product specification
Quad 2-input NOR gate
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Inputs accepts voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY H L L L QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
74AHC02; 74AHCT02
TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 2.9 AHCT 3.8 3.0 4.0 8.0 ns pF pF pF UNIT
VI = VCC or GND 3.0 4.0 7.0
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1, 4, 10 and 13 2, 5, 8 and 11 3, 6, 9 and 12 7 14 SYMBOL 1Y to 4Y 1A to 4A 1B to 4B GND VCC DESCRIPTION data outputs data inputs data inputs ground (0 V) DC supply voltage
1999 Sep 23
2
Philips Semiconductors
Product specification
Quad 2-input NOR gate
ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC02D 74AHC02PW 74AHCT02D 74AHCT02PW
74AHC02; 74AHCT02
PACKAGES NORTH AMERICA PINS 74AHC02D 74AHC02PW DH 74AHCT02D 74AHCT02PW DH 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1
handbook, halfpage
1Y 1A 1B 2Y 2A 2B GND
1 2 3 4 5 6 7
MNA214
14 VCC 13 4Y 12 4B
handbook, halfpage
A Y B
MNA215
02
11 4A 10 3Y 9 3B
8 3A
Fig.1 Pin configuration.
Fig.2 Logic diagram (one gate).
handbook, halfpage
2 3
1
1
handbook, halfpage
2 3 5 6 8 9 11 12
1A 1B 2A 2B 3A 3B 4A 4B
1Y
1 5
1
4
2Y
4
6
3Y
10
8 9
1
10
4Y
13 11
MNA216
1
13
12
MNA217
Fig.3 Functional diagram.
Fig.4 IEC logic symbol.
1999 Sep 23
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range see DC and AC characteristics per device VCC = 5 V ±0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40
74AHC02; 74AHCT02
74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V °C
TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40
+125 -40 100 20 - -
+125 °C - 20 ns/V
tr,tf (t/f) input rise and fall rates
VCC = 3.3 V ±0.3 V - -
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage range DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature range power dissipation per package for temperature range: -40 to +125 °C; note 2 VI VCC + 0.5 V; note 1 -0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 ±20 ±25 ±75 500 V V mA mA mA mA mW
+150 °C
1999 Sep 23
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
DC CHARACTERISTICS
74AHC02; 74AHCT02
74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage; all outputs HIGH-level output voltage VI = VIH or VIL; IO = -50 µA VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage; all outputs LOW-level output voltage VI = VIH or VIL; IO = 50 µA VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (°C) -40 to +85 - - 0.5 0.9 1.65 - - - -40 to +125 UNIT - - 0.5 0.9 1.65 - - - V V V
MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V
3.85 -
3.85 -
3.85 -
2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3
2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 ±2.5 20 10
2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0
V
V
µA
VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 -
±0.25 - 2.0 10 - -
±10.0 µA 40 10 µA pF
1999 Sep 23
5
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