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Part: 74AHC139PWDH
Category:
Logic
-> Decoders/Demultiplexers
Description: 74AHC139; 74AHCT139; Dual 2-to-4 Line Decoder/demultiplexer;; Package: SOT109 (SO16), SOT403-1 (TSSOP16)
Company: Philips Semiconductors
Datasheet: Download 74AHC139PWDH datasheet File size : 275 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC139; 74AHCT139 Dual 2-to-4 line decoder/demultiplexer
Product specification File under Integrated Circuits, IC06 1999 Sep 01
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt trigger actions · Inputs accept voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 °C and -40 to +125 °C. DESCRIPTION
74AHC139; 74AHCT139
The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. The `139' is identical to the HEF4556 of the HE4000B family.
QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nAn to nYn nE to nYn CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 VI = VCC or GND CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.9 3.4 3.0 4.0 25.76 4.7 3.6 3.0 4.0 22.36 ns ns pF pF pF AHCT UNIT
1999 Sep 01
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FUNCTION TABLE See note 1. INPUTS nE H L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC139D 74AHC139PW 74AHCT139D 74AHCT139PW PINNING PIN 1 and 15 2 and 3 4, 5, 6 and 7 8 9, 10, 11 and 12 13 and 14 16 SYMBOL 1E and 2E 1A0 and 1A1 1Y0, 1Y1, Y2 and 1Y3 GND 2Y3, 2Y2, 2Y1 and 2Y0 2A1 and 2A0 VCC address inputs outputs (active LOW) ground (0 V) outputs (active LOW) address inputs DC supply voltage DESCRIPTION enable inputs (active LOW) PACKAGES NORTH AMERICA PINS 74AHC139D 74AHC139PW DH 74AHCT139D 74AHCT139PW DH 16 16 16 16 PACKAGE SO TSSOP SO TSSOP nA0 X L H L H nA1 X L L H H nY0 H L H H H nY1 H H L H H OUTPUTS nY2 H H H L H
74AHC139; 74AHCT139
nY3 H H H H L
MATERIAL plastic plastic plastic plastic
CODE SOT109-1 SOT403-1 SOT109-1 SOT403-1
1999 Sep 01
3
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74AHC139; 74AHCT139
handbook, halfpage
1E 1 1A0 2 1A1 3 1Y0 4 1Y1 5 1Y2 6 1Y3 7 GND 8
MNA465
16 VCC 15 2E 14 2A0
handbook, halfpage
1 1E 2 3 1Y0 1A0 1A1 1Y1 1Y2 1Y3 14 13 2Y0 2A0 2A1 2E 2Y1 2Y2 2Y3
4 5 6 7 12 11 10 9
139
13 2A1 12 2Y0 11 2Y1 10 2Y2 9 2Y3
15
MNA466
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage handbook, halfpage
1Y0 2 3 1A0 1A1 1Y1 1Y2 1Y3 1 1E
4 5 6 7
2 3 1
DX 0 0 01 G 3 1 2 3 DX 0 01 G 3 1 2 0 3
4 5 6 7 2 3 1 1 2 EN
X/Y 0 1 2 3 X/Y 0 1 2 EN 1 2 3
4 5 6 7
12 11 10 9 14 13 15
12 11 10 9
MNA467
14 13 15
2Y0 12 14 13 2A0 2A1 2Y1 11 2Y2 10 2Y3 15 2E
MNA468
9
(a)
(b)
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 01
4
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER DC supply voltage input voltage output voltage operating ambient temperature see DC and AC characteristics per device VCC = 5 ±0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 - - TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 100 20 4.5 0 0 -40 - -
74AHC139; 74AHCT139
74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 - 20 V V V °C ns/V
+125 -40
+125 °C
input rise and fall ratio VCC = 3.3 ±0.3 V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +125 °C; note 2 VI VCC + 0.5 V; note 1 -0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 ±20 ±25 ±75 500 V V mA mA mA mA mW
+150 °C
1999 Sep 01
5
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