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Part: 74AHCT138D
Category:
Logic
-> Decoders/Demultiplexers
Description: 74AHC138; 74AHCT138; 3-to-8 Line Decoder/demultiplexer; Inverting;; Package: SOT109 (SO16), SOT403-1 (TSSOP16)
Company: Philips Semiconductors
Datasheet: Download 74AHCT138D datasheet File size : 67 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting
Product specification Supersedes data of 1999 Mar 31 File under Integrated Circuits, IC06 1999 Sep 27
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Inputs accept voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. DESCRIPTION
74AHC138; 74AHCT138
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The `138' features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the `138' to a 1-of-32 (5 to 32 lines) decoder with just four `138' ICs and one inverter. The `138' can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The `138' is identical to the `238' but has inverting outputs.
TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay An to Yn propagation delay E3 to Yn; En to Yn input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V VI = VCC or GND 4.4 4.2 3.0 4.0 18 AHCT 4.4 4.3 3.0 4.0 23 ns ns pF pF pF UNIT
1999 Sep 27
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
FUNCTION TABLE See note 1. INPUT E1 H X X L L L L L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC138D 74AHC138PW 74AHCT138D 74AHCT138PW PINNING PIN 1, 2 and 3 4 and 5 6 7, 9, 10 11, 12, 13, 14 and 15 8 16 SYMBOL A0, A1 and A2 E1 and E2 E3 Y7 to Y0 GND VCC address inputs enable inputs (active LOW) enable input (active HIGH) outputs (active LOW) ground (0 V) DC supply voltage PACKAGES NORTH AMERICA PINS 74AHC138D 74AHC138PW DH 74AHCT138D 74AHCT138PW DH 16 16 16 16 PACKAGE SO TSSOP SO TSSOP E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUT Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H
74AHC138; 74AHCT138
Y5 H H H H H H H H L H H
Y6 H H H H H H H H H L H
Y7 H H H H H H H H H H L
MATERIAL plastic plastic plastic plastic
CODE SOT109-1 SOT403-1 SOT109-1 SOT403-1
DESCRIPTION
1999 Sep 27
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138; 74AHCT138
handbook, halfpage
A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 Y7 7 GND 8
MNA369
16 VCC 15 Y0 14 Y1
handbook, halfpage
1 2 3 E1 E2 E3
A0 A1 A2
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
MNA370
15 14 13 12 11 10 9 7
138
13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 4 5 6
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage handbook, halfpage
DX
0 1
15 14 13 12 11 10 9 7 4 5 6 & 1 2 3 1 2 4
X/Y
0 1 2 3 4 5 6
15 14 13 12 11 10 9 7 4 5 6 E1 E2 E3 1 2 3 A0 A1 A2 3-to-8 DECODER ENABLE EXITING
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
15 14 13 12 11 10 9 7
1 2 3
0 G 2 0 7
2 3 4
4 5 6
&
5 6 7
EN 7
MNA371
(a)
(b)
MNA372
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 27
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range see DC and AC characteristics per device VCC = 5 V ±0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40 TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40
74AHC138; 74AHCT138
74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V °C
+125 -40 100 20 - -
+125 °C - 20 ns/V
tr,tf (t/f) input rise and fall rates
VCC = 3.3 V ±0.3 V - -
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage range DC input diode current DC output diode current DC VCC or GND current storage temperature range power dissipation per package for temperature range: -40 to +125 °C; note 2 VI VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 ±20 ±25 ±75 500 V V mA mA mA mA mW
DC output source or sink current -0.5 V < VO < VCC + 0.5 V
+150 °C
1999 Sep 27
5
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