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Part: 74AHCT157PWDH
Category:
Logic
-> Multiplexers/Demultiplexers
-> Multiplexers
Description: 74AHC157; 74AHCT157; Quad 2-input Multiplexer;; Package: SOT109-1 (SO16), SOT403-1 (TSSOP16)
Company: Philips Semiconductors
Datasheet: Download 74AHCT157PWDH datasheet File size : 67 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC157; 74AHCT157 Quad 2-input multiplexer
Product specification File under Integrated Circuits, IC06 1999 Sep 24
Philips Semiconductors
Product specification
Quad 2-input multiplexer
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Multiple input enable for easy expansion · Ideal for memory chip select decoding · Inputs accept voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 and +125 °C. FUNCTION TABLE See note 1. INPUT E H L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC157D 74AHC157PW 74AHCT157D 74AHCT157PW PACKAGES NORTH AMERICA PINS 74AHC157D 74AHC157PW DH 74AHCT157D 74AHCT157PW DH 16 16 16 16 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic S X L L H H nI0 X L H X X nI1 X X X L H OUTPUT nY L L H L H DESCRIPTION
74AHC157; 74AHCT157
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the `157'. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The `157' is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S. The logic equations are: 1Y = E × (1I1 × S + 1I0 × S); 2Y = E × (2I1 × S + 2I0 × S); 3Y = E × (3I1 × S + 3I0 × S); 4Y = E × (4I1 × S + 4I0 × S). The `157' is identical to the `158' but has non-inverting (true) outputs.
CODE SOT109-1 SOT403-1 SOT109-1 SOT403-1
1999 Sep 24
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nI0, nI1 to nY S to nY E to nY CI CO CPD input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 4 outputs switching via S 1 output switching via I Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1 2, 5, 11 and 14 3, 6, 10 and 13 4, 7, 9 and 12 8 15 16 S 1I0 to 4I0 1I1 to 4I1 1Y to 4Y GND E VCC SYMBOL 31 13 41 16 CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V CL = 15 pF; VCC = 5 V VI = VCC or GND 3.2 4.5 3.7 3.0 4.0 3.4 5.1 4.0 3.0 4.0 CONDITIONS AHC
74AHC157; 74AHCT157
UNIT AHCT ns ns ns pF pF pF pF
DESCRIPTION common data select input data inputs from source 0 data inputs from source 1 multiplexer outputs ground (0 V) enable input (active LOW) DC supply voltage
1999 Sep 24
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74AHC157; 74AHCT157
handbook, halfpage
S1 1I0 2 1I1 3 1Y 4
16 VCC 15 E 14 4 I0
handbook, halfpage
2
3
5
6
11
10
14
13
157
2 I0 5 2 I1 6 2Y 7 GND 8
MNA480
13 4 I1 12 4Y 11 3 I0 10 3 I1 9 3Y
1I0 1I1 2 I0 2 I1 3 I0 3 I1 4 I0 4 I1 1 15 S E 1Y 4 2Y 7 3Y 9 4Y 12
MNA481
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1 15
handbook, halfpage
G1 EN
2 3 5 MUX 4 6 11 10 14 13 12
1I0 1I1 2 I0 2 I1 3 I0 3 I1 4 I0 4 I1 SELECTOR MULTIPLEXER OUTPUTS
1Y
4
2 3 5 6 11 10 14 13
1 1
2Y
7
7
3Y
9
9
4Y 12
S
MNA482
E 15
MNA483
1
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 24
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer
74AHC157; 74AHCT157
handbook, halfpage
S
E
1I1 1I0
1Y
2 I1 2 I0
2Y
3 I1 3 I0
3Y
4 I1 4 I0
4Y
MNA484
Fig.5 Logic diagram.
1999 Sep 24
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
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