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Part: 74AHCT164PW
Category:
Logic
-> Registers
-> Shift Registers
Description: 74AHC164; 74AHCT164; 8-bit Serial-in/parallel-out Shift Register;; Package: SOT108-1 (SO14), SOT402-1 (TSSOP14)
Company: Philips Semiconductors
Datasheet: Download 74AHCT164PW datasheet File size : 67 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register
Product specification File under Integrated Circuits, IC06 2000 Aug 15
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Inputs accept voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 °C and from -40 to +125 °C. DESCRIPTION
74AHC164; 74AHCT164
The 74AHC/AHCT164 shift registers are high-speed silicon-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT164 input signals are 8-bit serial through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is a logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge. A LOW level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Qn MR to Qn CI fmax CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. input capacitance maximum clock frequency power dissipation capacitance VI = VCC or GND CL = 15 pF; VCC = 5 V CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 4.5 4.0 3 175 48 3.4 3.5 3 175 51 ns ns pF MHz pF AHCT UNIT
2000 Aug 15
2
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
FUNCTION TABLE See note 1.
74AHC164; 74AHCT164
INPUTS OPERATING MODES MR reset (clear) shift L H H H H Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; = LOW-to-HIGH transition; X = don't care; CP X Dsa X l l h h Dsb X l h l h
OUTPUTS Q0 L L L L H Q1-Q7 L-L q0-q6 q0-q6 q0-q6 q0-q6
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. ORDERING INFORMATION PACKAGES TYPE NUMBER 74AHC164D 74AHC164PW 74AHCT164D 74AHCT164PW TEMPERATURE RANGE -40 to +125 °C PINS 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1
2000 Aug 15
3
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
PINNING PIN 1, 2 3, 4, 5, 6, 10, 11, 12, 13 7 8 9 14 Dsa, Dsb Q0 to Q7 GND CP MR VCC SYMBOL data input outputs
74AHC164; 74AHCT164
DESCRIPTION
ground (0 V) clock input (LOW-to-HIGH, edge-triggered) master reset input (active LOW) DC supply voltage
handbook, halfpage
handbook, halfpage
Dsa Dsb Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7
MNA596
14 VCC 13 Q7 12 Q6
1 Dsa 2 Dsb
Q0 Q1 Q2 Q3
3 4 5 6 10 11 12 13
MNA597
164
11 Q5 8 10 Q4 9 8 MR CP 9 CP
Q4 Q5
MR
Q6 Q7
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2000 Aug 15
4
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
handbook, halfpage
8 9
SRG8 C1/ R
handbook, halfpage
1 2
&
1D
3 4 5 6 10 11
1 2 8 9
Dsa Dsb CP MR
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MNA598
3
4
5
6
10
11
12
13
12 13
MNA599
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
Dsa D Dsb Q D Q D Q D Q D Q D Q D Q D Q CP FF1 RD CP FF2 RD CP FF3 RD CP FF4 RD CP FF5 RD CP FF6 RD CP FF7 RD CP FF8 RD
CP MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
MNA600
Q7
Fig.5 Logic diagram.
2000 Aug 15
5
Others parts begin by 74
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