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Details, datasheet, quote on part number:74ALS161B
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| Part: | 74ALS161B |
| Category: | Logic => Counters => CMOS/BiCMOS->LV/LVQ/LVX Family->Low Voltage |
| Description: | 74ALS161B/74ALS163B; 4-bit Binary Counter |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74ALS161B datasheet File size : 138 kB |
| Request For quote: | Find where to buy 74ALS161B
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Datasheet text preview:
INTEGRATED CIRCUITS
74ALS161B/74ALS163B 4-bit binary counter
Product specification IC05 Data Handbook 1991 Feb 08
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
FEATURES
74ALS161B/74ALS163B
4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset
DESCRIPTION
Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
· Synchronous counting and loading · Two count enable inputs for n-bit cascading · Positive edge-triggered clock · Asynchronous reset (74ALS161B) · Synchronous reset (74ALS163B) · High speed synchronous expansion · Typical count rate of 140MHz
TYPICAL SUPPLY CURRENT (TOTAL) 10mA 10mA
TYPE 74ALS161B 74ALS163B
TYPICAL fMAX 140MHz 140MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS161BN, 74ALS163BN 74ALS161BD, 74ALS163BD 74ALS161BDB, 74ALS163BDB DRAWING NUMBER SOT38-4 SOT109-1 SOT338-1
16-pin plastic DIP 16-pin plastic SO 16-pin plastic SSOP Type II
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 D3 CEP CET CP PE MR SR Q0 Q3 TC Data inputs Count enable parallel input (active-Low) Count enable trickle input (active-Low) Clock input (active rising edge) Parallel enable input (active-Low) Asynchronous master reset input (active-Low) for 74ALS161B Asynchronous reset input (active-Low) for 74ALS163B Flip-flop outputs Terminal count output (active-Low) DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 20/80 20/80 LOAD VALUE HIGH/LOW 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 20µA/0.1mA 0.4mA/8mA 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08
2
8531350 01670
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
SF00664
APPLICATIONS
VCC
PE CEP CET CLOCK CP SR
D0 D1
D2 D3
74ALS163B
TC
Q0 Q1 Q2 Q3
SC00086
Figure 1. Maximum Count Modifying Scheme Terminal Count = 6
H H = Enable count or L L = Disable count
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
CP
SC00087
Figure 2. Synchronous Multistage Counting Scheme
1991 Feb 08
3
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
PIN CONFIGURATION 74ALS161B
MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
PIN CONFIGURATION 74ALS163B
SR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
SF00656
SF00657
LOGIC SYMBOL 74ALS161B
3 4 5 6
LOGIC SYMBOL 74ALS163B
3 4 5 6
9 7 10 2 1
PE CEP CET CP MR
D0
D1
D2
D3
9 7 TC 15 10 2
PE CEP CET CP SR
D0
D1
D2
D3
TC
15
Q0
Q1
Q2
Q3
1
Q0
Q1
Q2
Q3
VCC = Pin 16 GND = Pin 8
14
13
12
11
VCC = Pin 16 GND = Pin 8
14
13
12
11
SF00658
SF00659
IEC/IEEE SYMBOL 74ALS161B
1 9 7 10 2 R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
IEC/IEEE SYMBOL 74ALS163B
1 9 7 10 2 2R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
3 4 5 6
1,2 D
14 13 12 11 15
3 4 5 6
1,2 D
14 13 12 11 15
4 CT=15
4 CT=15
SF00660
SF00661
1991 Feb 08
4
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
LOGIC DIAGRAM 74ALS161B
CP MR 2 1
PE CET CEP D0
9 10 7 3 DRQ
CP
Q
14
Q0
D1
4 DRQ
CP
Q
13
Q1
D2
5 DRQ
CP
Q
12
Q2
D3
6 DRQ
CP
Q
11
Q3
15 VCC = Pin 16 GND = Pin 8
TC
SF00662
MODE SELECTION FUNCTION TABLE 74ALS161B
INPUTS MR L H H H h h H= h= L= l= qn = X= (a) = = CP X X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X L L H count qn qn OUTPUTS Qn TC L L (a) (a) (a) L Reset (clear) Parallel load load Count Hold (do nothing) (do nothing) OPERATING MODE MODE
High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don't care The output is High when CET is High and the counter is at terminal count (HHHH) Low-to-High clock transition
1991 Feb 08
5
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