Digchip : Database on electronics components
Electronics components database



Details, datasheet, quote on part number: 74ALVCH162601DGG
 
 
Part number74ALVCH162601DGG
CategoryLogic => Transceivers
Description74ALVCH162601; 18-bit Universal Bus Transceiver With 30 Ohm Termination Resistor; 3-state;; Package: SOT364-1 (TSSOP56)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74ALVCH162601DGG datasheet
Request For QuoteFind where to buy 74ALVCH162601DGG
 


 
Specifications, Features, Applications

Product specification File under Integrated Circuits, IC24 1999 Oct 14

FEATURES· Complies with JEDEC standard no. 8-1A· CMOS low power consumption· Direct interface with TTL levels· MULTIBYTETM flow-through standard pin-out architecture· Low inductance multiple VCC and ground pins for minimum noise and ground bounce· All data inputs have bus hold circuitry· Integrated 30 termination resistors. DESCRIPTION

The an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high-impedance state during power-down, OEBA and OEAB should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The 74ALVCH162601 is designed with 30 series resistors in both HIGH or LOW output stage. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; = 2.5 ns. SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER propagation delay An, Bn to Bn, An input/output capacitance input capacitance power dissipation capacitance per latch notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD fi + (CL VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition VI = GND to VCC. 3 pF CONDITIONS = 30 pF; VCC = 50 pF; VCC 3.3 V TYPICAL ns pF UNIT

OUTPUTS CEXX Note = AB for A-to-B direction, BA for B-to-A direction; H = HIGH voltage level; L = LOW voltage level; h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CPXX; l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CPXX; X = don't care; = LOW-to-HIGH level transition; = no change; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE +85 °C PINS 56 PACKAGE TSSOP MATERIAL plastic OEXX LEXX CPXX An, L NC

STATUS disabled transparent hold clock and display hold



Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74ALVCH162827 74ALVCH162827; 20-bit Buffer/line Driver, Non-inverting, With 30 Ohm Termination Resistors (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16373 74ALVCH16373; 2.5 V / 3.3 V 16-bit D-type Transparent Latch (3-State);; Package: SOT362-1 (TSSOP48), SOT370-1 (SSOP48)
74ALVCH16374 74ALVCH16374; 2.5 V / 3.3 V 16-bit Edge-triggered D-type Flip-flop (3-State);; Package: SOT370-1 (SSOP48)
74ALVCH16500 74ALVCH16500; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16501 74ALVCH16501; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16540 74ALVCH16540; 2.5 V / 3.3 V 16-bit Buffer/line Driver, Inverting, 5 V Input Tolerant (3-State);; Package: SOT370-1 (SSOP48)
74ALVCH16543 74ALVCH16543; 16-bit D-type Registered Transceiver; 3-state;; Package: SOT364-1 (TSSOP56)
74ALVCH16600 74ALVCH16600; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16601 74ALVCH16601; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16623 74ALVCH16623; 16-bit Transceiver With Dual Enable; 3-state;; Package: SOT362-1 (TSSOP48)
74ALVCH16646 74ALVCH16646; 16-bit Transceiver/register (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH1665 216-bit Transceiver/register With Dual Enable (3-state)
74ALVCH16652 74ALVCH16652; 16-bit Transceiver/register With Dual Enable; 3-state;; Package: SOT364-1 (TSSOP56)
74ALVCH16821 74ALVCH16821; 20-bit Bus-interface D-type Flip-flop' Positive-edge Trigger (3-State);; Package: SOT371-1 (SSOP56)
74ALVCH16823 74ALVCH16823; 18-bit Bus-interface D-type Flip-flop With Reset And Enable (3-State);; Package: SOT371-1 (SSOP56)
74ALVCH16825 74ALVCH16825; 18-bit Buffer/driver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16827 74ALVCH16827; 20-bit Buffer/line Driver, Non-inverting (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16832 74ALVCH16832; 7-bit to 28-bit Address Register/driver With 3-state Outputs;; Package: SOT646-1 (TSSOP64)
74ALVCH16841 74ALVCH16841; 20-bit Bus Interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16843 74ALVCH16843; 18-bit Bus-interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16952 74ALVCH16952; 16-bit Registered Transceiver (3-State);; Package: SOT364-1 (TSSOP56)