Product specification File under Integrated Circuits, IC24 1999 Oct 14
FEATURES· Complies with JEDEC standard no. 8-1A· CMOS low power consumption· Direct interface with TTL levels· MULTIBYTETM flow-through standard pin-out architecture· Low inductance multiple VCC and ground pins for minimum noise and ground bounce· All data inputs have bus hold circuitry· Integrated 30 termination resistors. DESCRIPTION
The an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high-impedance state during power-down, OEBA and OEAB should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The 74ALVCH162601 is designed with 30 series resistors in both HIGH or LOW output stage. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; = 2.5 ns. SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER propagation delay An, Bn to Bn, An input/output capacitance input capacitance power dissipation capacitance per latch notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD fi + (CL VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition VI = GND to VCC. 3 pF CONDITIONS = 30 pF; VCC = 50 pF; VCC 3.3 V TYPICAL ns pF UNIT
OUTPUTS CEXX Note = AB for A-to-B direction, BA for B-to-A direction; H = HIGH voltage level; L = LOW voltage level; h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CPXX; l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CPXX; X = don't care; = LOW-to-HIGH level transition; = no change; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE +85 °C PINS 56 PACKAGE TSSOP MATERIAL plastic OEXX LEXX CPXX An, L NC
STATUS disabled transparent hold clock and display hold