Details, datasheet, quote on part number: 74ALVCH16373DL
CategoryLogic => Latches
Description74ALVCH16373; 2.5 V / 3.3 V 16-bit D-type Transparent Latch (3-State);; Package: SOT362-1 (TSSOP48), SOT370-1 (SSOP48)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74ALVCH16373DL datasheet
Cross ref.Similar parts: 74ALVCH16373PV, 74VCX16373DL, SN74ALVCH16373DL, 74AC16245, CY74FCT16240T, SN74ABT162244, SN74ALVC16244A, SN74ALVC16334, SN74ALVCH162244, SN74ALVCH162373
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Features, Applications

Product specification Supersedes data of 1998 Jun 29 IC24 Data Handbook 1999 Sep 20

Wide supply voltage range to 3.6V Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise

Direct interface with TTL levels All data inputs have bus hold Output drive capability 50 transmission lines @ 85C Current drive 3.0 V


The a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

GND = 0V; Tamb tf 2.5ns SYMBOL PARAMETER Propagation g delay to Qn tPHL/tPLH Propagation delay to Qn Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF VCC = 30pF VCC = 50pF TYPICAL pF ns UNIT

NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD + S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 fo) = sum of outputs.


Data inputs/outputs Ground (0V) Positive supply voltage Data inputs/outputs Output enable input (active LOW) Latch enable input (active HIGH) Data inputs Data inputs Latch enable input (active HIGH)

FUNCTION TABLE (per section of eight bits)

INPUTS OPERATING MODES nOE Enable and read register (transparent mode) Latch and read register (hold mode) Latch register and disable outputs nLE nDn INTERNAL LATCHES OUTPUTS nQn

= HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = don't care = high impedance OFF-state


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