Details, datasheet, quote on part number: 74ALVCH16374
Part74ALVCH16374
CategoryLogic => Flip-Flops
Description74ALVCH16374; 2.5 V / 3.3 V 16-bit Edge-triggered D-type Flip-flop (3-State);; Package: SOT370-1 (SSOP48)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74ALVCH16374 datasheet
Cross ref.Similar parts: 74ALVCH16374DGG, 74ALVCH16374DT, 74ALVCH16374DTR, HD74ALVCH162374, HD74ALVCH16374, IDT74ALVC16374PA, IDT74ALVCH162374PA, IDT74ALVCH16374PA, PI74ALVCH16374A, SN74ALVC16374DGGR
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Features, Applications

Product specification Supersedes data of 1997 Mar 21 IC24 Data Handbook 1998 Jun 18
FEATURES

Wide supply voltage range 3.6 V Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise

Direct interface with TTL levels All data inputs have bushold Output drive capability 50 transmission lines @ 85C Current drive 3.0 V

DESCRIPTION

The a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided per 8-bit section. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

GND = 0V; Tamb 2.5 ns SYMBOL tPHL/tPLH fMAX CI CPD PARAMETER Propagation delay to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip flip-flop flop VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF VCC = 2.5V VCC = 3.3V TYPICAL UNIT ns MHz pF

NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD + S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 fo) = sum of outputs.

PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85C OUTSIDE NORTH AMERICA DL 74ALVCH16374 DGG NORTH AMERICA DL ACH16374 DGG DWG NUMBER SOT370-1 SOT362-1

3-State flip-flop outputs Ground (0V) Positive supply voltage 3-State flip-flop outputs Output enable input (active LOW) Clock input Data inputs Data inputs Clock input

INPUTS OPERATING MODES Load and read register Load register and disable outputs CP Dn INTERNAL FLIP-FLOPS OUTPUTS to Q7

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state = LOW-to-HIGH CP transition


 

Related products with the same datasheet
74ALVCH16374DGG
74ALVCH16374DL
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74ALVCH16374DGG 74ALVCH16374; 2.5 V / 3.3 V 16-bit Edge-triggered D-type Flip-flop (3-State);; Package: SOT370-1 (SSOP48)
74ALVCH16500 74ALVCH16500; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16501 74ALVCH16501; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16540 74ALVCH16540; 2.5 V / 3.3 V 16-bit Buffer/line Driver, Inverting, 5 V Input Tolerant (3-State);; Package: SOT370-1 (SSOP48)
74ALVCH16543 74ALVCH16543; 16-bit D-type Registered Transceiver; 3-state;; Package: SOT364-1 (TSSOP56)
74ALVCH16600 74ALVCH16600; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16601 74ALVCH16601; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16623 74ALVCH16623; 16-bit Transceiver With Dual Enable; 3-state;; Package: SOT362-1 (TSSOP48)
74ALVCH16646 74ALVCH16646; 16-bit Transceiver/register (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH1665 216-bit Transceiver/register With Dual Enable (3-state)
74ALVCH16652 74ALVCH16652; 16-bit Transceiver/register With Dual Enable; 3-state;; Package: SOT364-1 (TSSOP56)
74ALVCH16821 74ALVCH16821; 20-bit Bus-interface D-type Flip-flop' Positive-edge Trigger (3-State);; Package: SOT371-1 (SSOP56)
74ALVCH16823 74ALVCH16823; 18-bit Bus-interface D-type Flip-flop With Reset And Enable (3-State);; Package: SOT371-1 (SSOP56)
74ALVCH16825 74ALVCH16825; 18-bit Buffer/driver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16827 74ALVCH16827; 20-bit Buffer/line Driver, Non-inverting (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16832 74ALVCH16832; 7-bit to 28-bit Address Register/driver With 3-state Outputs;; Package: SOT646-1 (TSSOP64)
74ALVCH16841 74ALVCH16841; 20-bit Bus Interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16843 74ALVCH16843; 18-bit Bus-interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH16952 74ALVCH16952; 16-bit Registered Transceiver (3-State);; Package: SOT364-1 (TSSOP56)
74ALVCH32501 74ALVCH32501; 36-bit Universal Bus Transceiver With Direction Pin; 5 V Tolerant; 3-state;; Package: SOT537-1 (LFBGA114)
74ALVCHS162830 74ALVCHS162830; 18-bit to 36-bit Address Driver With Bus Hold (3-State);; Package: SOT647-1 (TSSOP80)
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