|Category||Logic => Flip-Flops|
|Description||74ALVCH16374; 2.5 V / 3.3 V 16-bit Edge-triggered D-type Flip-flop (3-State);; Package: SOT370-1 (SSOP48)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74ALVCH16374 datasheet
|Cross ref.||Similar parts: 74ALVCH16374DGG, 74ALVCH16374DT, 74ALVCH16374DTR, HD74ALVCH162374, HD74ALVCH16374, IDT74ALVC16374PA, IDT74ALVCH162374PA, IDT74ALVCH16374PA, PI74ALVCH16374A, SN74ALVC16374DGGR|
Product specification Supersedes data of 1997 Mar 21 IC24 Data Handbook 1998 Jun 18
Wide supply voltage range 3.6 V Complies with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise
Direct interface with TTL levels All data inputs have bushold Output drive capability 50 transmission lines @ 85°C Current drive 3.0 VDESCRIPTION
The a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided per 8-bit section. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
GND = 0V; Tamb 2.5 ns SYMBOL tPHL/tPLH fMAX CI CPD PARAMETER Propagation delay to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip flip-flop flop VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF VCC = 2.5V VCC = 3.3V TYPICAL UNIT ns MHz pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85°C OUTSIDE NORTH AMERICA DL 74ALVCH16374 DGG NORTH AMERICA DL ACH16374 DGG DWG NUMBER SOT370-1 SOT362-1
3-State flip-flop outputs Ground (0V) Positive supply voltage 3-State flip-flop outputs Output enable input (active LOW) Clock input Data inputs Data inputs Clock input
INPUTS OPERATING MODES Load and read register Load register and disable outputs CP Dn INTERNAL FLIP-FLOPS OUTPUTS to Q7
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state ° = LOW-to-HIGH CP transition
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