|Category||Logic => Transceivers|
|Description||74ALVCH16501; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74ALVCH16501 datasheet
Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 29
Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive 3.0 V Universal bus transceiver with D-type latches and D-type flip-flopscapable of operating in transparent, latched or clocked mode.
The an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low). To ensure the high impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All inputs have bushold circuitry Output drive capability 50 transmission lines 85°C 3-State non-inverting outputs for bus oriented applications
GND = 0V; Tamb = 2.5ns SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER Propagation delay An, Bn to Bn, An Input/output capacitance Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF TYPICAL UNIT pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.
PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85°C OUTSIDE NORTH AMERICA 74ALVCH16501 DGG DWG NUMBER SOT364-1Ground (0V) Positive supply voltage Output enable B-to-A Latch enable B-to-A Clock input B-to-A
OEAB CPAB LEAB C3 G2 OEBA CPBA LEBA C6 G5
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