|Category||Logic => Transceivers|
|Description||74ALVCH16501; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74ALVCH16501 datasheet
Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 29
Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive 3.0 V Universal bus transceiver with D-type latches and D-type flip-flopscapable of operating in transparent, latched or clocked mode.
The an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low). To ensure the high impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All inputs have bushold circuitry Output drive capability 50 transmission lines 85°C 3-State non-inverting outputs for bus oriented applications
GND = 0V; Tamb = 2.5ns SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER Propagation delay An, Bn to Bn, An Input/output capacitance Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF TYPICAL UNIT pF F
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.
PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85°C OUTSIDE NORTH AMERICA 74ALVCH16501 DGG DWG NUMBER SOT364-1Ground (0V) Positive supply voltage Output enable B-to-A Latch enable B-to-A Clock input B-to-A
OEAB CPAB LEAB C3 G2 OEBA CPBA LEBA C6 G5
|Related products with the same datasheet|
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
|74ALVCH16501DGG 74ALVCH16501; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16540 74ALVCH16540; 2.5 V / 3.3 V 16-bit Buffer/line Driver, Inverting, 5 V Input Tolerant (3-State);; Package: SOT370-1 (SSOP48)|
|74ALVCH16543 74ALVCH16543; 16-bit D-type Registered Transceiver; 3-state;; Package: SOT364-1 (TSSOP56)|
|74ALVCH16600 74ALVCH16600; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16601 74ALVCH16601; 18-bit Universal Bus Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16623 74ALVCH16623; 16-bit Transceiver With Dual Enable; 3-state;; Package: SOT362-1 (TSSOP48)|
|74ALVCH16646 74ALVCH16646; 16-bit Transceiver/register (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH1665 216-bit Transceiver/register With Dual Enable (3-state)|
|74ALVCH16652 74ALVCH16652; 16-bit Transceiver/register With Dual Enable; 3-state;; Package: SOT364-1 (TSSOP56)|
|74ALVCH16821 74ALVCH16821; 20-bit Bus-interface D-type Flip-flop' Positive-edge Trigger (3-State);; Package: SOT371-1 (SSOP56)|
|74ALVCH16823 74ALVCH16823; 18-bit Bus-interface D-type Flip-flop With Reset And Enable (3-State);; Package: SOT371-1 (SSOP56)|
|74ALVCH16825 74ALVCH16825; 18-bit Buffer/driver (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16827 74ALVCH16827; 20-bit Buffer/line Driver, Non-inverting (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16832 74ALVCH16832; 7-bit to 28-bit Address Register/driver With 3-state Outputs;; Package: SOT646-1 (TSSOP64)|
|74ALVCH16841 74ALVCH16841; 20-bit Bus Interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16843 74ALVCH16843; 18-bit Bus-interface D-type Latch (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH16952 74ALVCH16952; 16-bit Registered Transceiver (3-State);; Package: SOT364-1 (TSSOP56)|
|74ALVCH32501 74ALVCH32501; 36-bit Universal Bus Transceiver With Direction Pin; 5 V Tolerant; 3-state;; Package: SOT537-1 (LFBGA114)|
|74ALVCHS162830 74ALVCHS162830; 18-bit to 36-bit Address Driver With Bus Hold (3-State);; Package: SOT647-1 (TSSOP80)|
|74ALVCHS16830 74ALVCHS16830; 18-bit to 36-bit Address Driver With Bus Hold (3-State);; Package: SOT647-1 (TSSOP80)|
|74ALVCHT16835 74ALVCHT16835; 18-bit Registered Driver (3-State);; Package: SOT481-2 (TSSOP56)|
74ACT16254 : Multiplexers->CMOS/BiCMOS->AC/ACT Family. 16-bit Address/data Multiplexer With 3-state Outputs: 16-bit.
74HC/HCT11 : CMOS/BiCMOS->HC/HCT Family. Triple 3-input And Gate. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family s The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines Product File under Integrated Circuits, IC06 December 1990 Output capability: standard ICC category: SSI GENERAL The 74HC/HCT11 are high-speed Si-gate CMOS.
75ACT16623 : 16-bit Bus Transceivers With 3-state Outputs. Members of the Texas Instruments Widebus TM Family Inputs are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using.
CD54HCT243 : Bus Oriented Circuits. High Speed CMOS Logic Quad-bus Transceiver With Three-state Outputs.
HD74LV1G126A : . Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
HS1-26C32RH : Radiation Hardened Quad Differential Line Receiver. Radiation Hardened Quad Differential Line Receiver AIN 1 AIN 2 AOUT 3 ENABLE 4 COUT 5 CIN 6 CIN 7 16 VDD 15 BIN 14 BIN 13 BOUT 12 ENABLE 11 DOUT 10 DIN 9 DIN 1.2 Micron Radiation Hardened CMOS - Total Dose to 300K RAD (Si) Latchup Free EIA RS-422 Compatible Outputs CMOS Compatible Inputs Input Fail Safe Circuitry High Impedance Inputs when Disabled.
IDT74FCT3574 : CMOS/BiCMOS->FCT/FCT-T Family. 3.3v CMOS Octal D Register (3-state).
ISP1161 : Full-speed Universal Serial Bus Single-chip Host And Device Controller.
MC100LVEL56DWR2 : Multiplexers. 3.3V Ecl Dual Differential 2:1 Multiplexer, Package: Soic, Pins=20.
MC74LVX8053DTR2 : Analog Switches. Analog Multiplexer/Demultiplexer, Package: Tssop, Pins=16.
PI74FCT2827T : CMOS/BiCMOS->FCT/FCT-T Family. 10-Bit Buffer. PI74FCT827/828/2827/2828T are pin compatible with bipolar FASTTM Series at a higher speed and lower power consumption 25 series resistor on all outputs (FCT2XXX only) TTL input and output levels Low ground bounce outputs Extremely low static power Hysteresis on all inputs Industrial operating temperature range: to +85°C Packages available: 24-pin 300-mil.
PI74LPT240 : CMOS/BiCMOS->ABT/BCT Family. Inverting Octal Buffer/line Driver. PI74LPT240 Fast CMOS 3.3V 8-Bit Inverting Buffer Line Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed-Signal Mode Operation Input can or 5V Output can 3V or connected to 5V bus Advanced.
SN74ACT7805-15DL : Synchronous FIFOs. ti SN74ACT7805, 256 X 18 Synchronous Fifo Memory. Member of the Texas Instruments WidebusTM Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 256 Words by 18 Bits Low-Power Advanced CMOS Technology Half-Full Flag and Programmable.
SN74ALS867A : Bipolar->AS Family. 8-bit Synchronous Up/down Counter. Fully Programmable With Synchronous Counting and Loading SN74ALS867A and AS867 Have Asynchronous Clear; SN74ALS869 and AS869 Have Synchronous Clear Fully Independent Clock Circuit Simplifies Use Ripple-Carry Output for n-Bit Cascading Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic.
SN74LVC1G125DBVR : Single Gates. ti SN74LVC1G125, Single Bus Buffer Gate With 3-State Outputs.
TC74HC03AF(TP1) : HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14. s: Gate Type: NAND ; Supply Voltage: 5V ; Output Type: Open Drain ; Logic Family: CMOS ; Inputs: 2 ; Propagation Delay: 19 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Pin Count: 14 ; IC Package Type: SOIC, Other, 0.300 INCH, PLASTIC, SOIC-14.
935063110118 : LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NOR GATE, PDSO14. s: Gate Type: NOR ; Supply Voltage: 3.3V ; Logic Family: CMOS ; Inputs: 2 ; Propagation Delay: 26 ns ; Operating Temperature: -40 to 125 C (-40 to 257 F) ; Pin Count: 14 ; IC Package Type: Other, 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14.