· Wide supply voltage range 3.6 V· Complies with JEDEC standard no. 8-1A· CMOS low power consumption· MULTIBYTETM flow-through standard pin-out architecture· Low inductance multiple VCC and ground pins for minimum noise

· Direct interface with TTL levels· Bus hold on all data inputs eliminates the need for external pull-up

The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The a 16-bit inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OEn and 2OEn. A HIGH on nOEn causes the outputs to assume a high impedance OFF-state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.

GND = 0V; Tamb tf 2.5ns SYMBOL PARAMETER Propagation delay to 2Yn Input capacitance Power dissipation capacitance per buffer VI = GND to VCC1 Outputs enabled Outputs disabled = 50pF VCC = 30pF VCC = 2.5V CONDITIONS TYPICAL UNIT ns pF

NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.

PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85°C OUTSIDE NORTH AMERICA DL 74ALVCH16540 DGG NORTH AMERICA DL ACH16540 DGG DWG NUMBER SOT370-1 SOT362-1