Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Sep 20
FEATURES· Complies with JEDEC standard no. 8-1A· CMOS low power consumption· Direct interface with TTL levels· MULTIBYTETM flow-through standard pin-out architecture· All data inputs have bus hold circuitry· Output drive capability 50 transmission lines at 85 °C· Current drive 3.0 V. DESCRIPTION
The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This 16-bit bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (nOEAB, nOEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in this transceiver configuration. Thus, when all control inputs are enabled and all other data sources to the four sets of the bus lines are at high-impedance OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes appearing on the two double sets of buses will be complementary. This device can be used as two 8-bit transceivers or one 16-bit transceiver. To ensure the high-impedance state during power-on or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; = 2.5 ns. SYMBOL tPHL/tPLH CI/O CI CPD PARAMETER propagation delay nAn, nBn to nBn, nAn input/output capacitance input capacitance power dissipation capacitance per buffer notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD fi + (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in Volts; (CL VCC2 × fo) = sum of outputs. 2. The condition VI = GND to VCC. 1999 Sep pF CONDITIONS = 30 pF; VCC = 50 pF; VCC 3.3 V TYPICAL ns pF UNIT
ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74ALVCH16623DGG FUNCTION TABLE See note 1. INPUTS nOEAB Note H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. PINNING PIN SYMBOL to 1B7 GND VCC to 1A0 nOEBA nAn A=B inputs Z A=B +85 °C PINS 48 PACKAGE TSSOP
DESCRIPTION output enable input (active HIGH) data inputs/outputs ground V) DC supply voltage data inputs/outputs output enable input (active LOW) data inputs/outputs data inputs/outputs