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Details, datasheet, quote on part number: 74ALVCH16823DL
Part number74ALVCH16823DL
CategoryLogic => Flip-Flops
Description74ALVCH16823; 18-bit Bus-interface D-type Flip-flop With Reset And Enable (3-State);; Package: SOT371-1 (SSOP56)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74ALVCH16823DL datasheet
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Specifications, Features, Applications

74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State)

· Wide supply voltage range to 3.6V· Complies with JEDEC standard no. 8-1A.· CMOS low power consumption· Direct interface with TTL levels· Current drive 3.0 V· MultibyteTMflow-through standard pin-out architecture· Low inductance multiple VCC and GND pins to minimize noise and


The a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (CP) input, an output-enable (OE) input, a Master reset (MR) input and a clock-enable( CE) input are provided for each total 9-bit section. With the clock-enable (CE) input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. Taking CE HIGH disables the clock buffer, thus latching the outputs. Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock. When OE is LOW, the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

· All data inputs have bus hold· Output drive capability 50 transmission lines @ 85°C

GND = 0V; Tamb tf 2.5ns SYMBOL tPHL/tPLH Fmax CI CPD PARAMETER Propagation delay to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 30pF VCC = 50pF VCC = 30pF VCC = 50pF TYPICAL UNIT ns MHz pF

NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.


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