· Wide supply voltage range to 3.6V· Complies with JEDEC standard no. 8-1A· Wide supply voltage range to 3.6V· CMOS low power consumption· Direct interface with TTL levels· Universal bus transceiver with D-type latches and D-type flip-flops

The a 20-bit non-inverting buffer/driver with 3-State outputs for bus oriented applications. The 74ALVCH16827 consists of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and or 2OE1 and 2OE2) inputs must both be active. If either output enable input is high, the outputs of that 10-bit buffer section are in high impedance state. The 74ALVCH16827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

· MULTIBYTETM flow-through standard pin-out architecture· Low inductance multiple VCC and GND pins for minimum noise

· Current drive 3.0 V· All inputs have bus hold circuitry· Output drive capability 50 transmission lines 85°C· 3-State non-inverting outputs for bus oriented applications

GND = 0V; Tamb = 2.5ns SYMBOL PARAMETER Propagation delay tPHL/tPLH Qn CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er latch

NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD + S (CL VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage V; S (CL VCC2 × fo) = sum of outputs.

PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE to +85°C OUTSIDE NORTH AMERICA 74ALVCH16827 DGG NORTH AMERICA ACH16827 DGG DWG NUMBER SOT364-1