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Details, datasheet, quote on part number:74ALVCH32501EC
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| Part: | 74ALVCH32501EC |
| Category: | Logic => Transceivers |
| Description: | 74ALVCH32501; 36-bit Universal Bus Transceiver With Direction Pin; 5 V Tolerant; 3-state;; Package: SOT537-1 (LFBGA114) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74ALVCH32501EC datasheet File size : 98 kB |
| Request For quote: | Find where to buy 74ALVCH32501EC
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH32501 36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
Product specification File under Integrated Circuits, IC24 2000 Mar 16
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
FEATURES · 3-state non-inverting outputs for bus oriented applications · Wide supply voltage range of 1.2 to 3.6 V · Complies with JEDEC standard no. 8-1A · Current drive ±24 mA at 3.0 V · Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode · CMOS low power consumption · Direct interface with TTL levels · All inputs have bus-hold circuitry · Output drive capability 50 transmission lines at 85 °C · Plastic fine-pitch ball grid array package. DESCRIPTION The 74ALVCH32501 is a high-performance CMOS product designed for VCC operation at 2.5 and 3.3 V with I/O compatibility up to 5 V. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER propagation delay An to Bn; Bn to An input capacitance input/output capacitance power dissipation capacitance per latch VI = GND to VCC; note 1 outputs enabled outputs disabled Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL × VCC2 × fo) = sum of the outputs. CONDITIONS CL = 30 pF; VCC = 2.5 V CL = 50 pF; VCC = 3.3 V
74ALVCH32501
The 74ALVCH32501 can be used as two 18-bit transceivers or one 36-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CPAB and CPBA). For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When input LEAB is LOW, the A data is latched if input CPAB is held at a HIGH or LOW level. If input LEAB is LOW, the A data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When input OEAB is HIGH, the outputs are active. When input OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B, but uses inputs OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW). To ensure the high-impedance state during power-up or power-down, pin OEBA should be tied to VCC through a pull-up resistor and pin OEAB should be tied to GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sinking or current-sourcing capability of the driver.
TYP. 2.8 3.0 4.0 8.0 21 3 ns ns
UNIT
pF pF pF pF
2000 Mar 16
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
FUNCTION TABLE See notes 1 and 2. INPUT nOEAB L L L L L L H H H H H H H H Notes 1. A-to-B data flow is shown; B-to-A flow is similar but uses nOEBA, nLEBA and nCPBA. 2. H = HIGH voltage level; h = HIGH voltage level on set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level on set-up time prior to the enable or clock transition; NC = no change; X = don't care; = LOW-to-HIGH enable or clock transition; = HIGH-to-LOW enable or clock transition; Z = high impedance OFF-state. nLEAB H L L L H H L L L L nCPAB X X X H or L X X X X H or L H or L nAn X h l X h l H L h l h l X X INTERNAL REGISTERS X H L NC H L H L H L H L H L OUTPUT
74ALVCH32501
OPERATING MODE nBn Z Z Z Z Z Z H L H L H L H L disabled disabled; latch data disabled; hold data disabled; clock data transparent latch data and display clock data and display hold data and display
2000 Mar 16
3
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
ORDERING INFORMATION PACKAGE TYPE NUMBER 74ALVCH32501EC PINNING SYMBOL nAn nBn GND VCC nOEAB nOEBA nLEAB nLEBA nCPAB nCPBA data inputs data outputs ground (0 V) DC supply voltage output enable inputs A to B (active HIGH) output enable inputs B to A (active LOW) latch enable inputs A to B latch enable inputs B to A clock input A to B clock input B to A DESCRIPTION TEMPERATURE RANGE -40 to +85 °C PINS 114 PACKAGE LFBGA114
74ALVCH32501
MATERIAL plastic
CODE SOT537-1
handbook, full pagewidth 1B1 1B3 6
1B5 1B4 GND GND 1A4 1A5
1B7 1B6 VCC VCC 1A6 1A7
1B9 1B8 GND GND 1A8 1A9
1B11 1B10 GND GND 1A10 1A11
1B13 1B12 VCC VCC 1A12 1A13
1B14 1B15
1B16
n.c.
2B1 2B0 GND
2B3 2B2 GND
2B5 2B4 VCC VCC 2A4 2A5
2B7 2B6 GND GND 2A6 2A7
2B9 2B8 GND GND 2A8 2A9
2B11 2B10 VCC VCC 2A10 2A11
2B13 2B12
2B14
2B16 2B17
5 4 3 2 1
1B0 1CPAB
1B2 GND
1B17 2CPAB GND
2B15
GND 1CPBA
GND 2CPBA GND GND 2OE BA 2LE BA 2A12 2A13 2A15 2A14 2A17 2A16
1LEAB 1OEAB 1A0 1A1 1A2 1A3
GND 1OE BA 1LE BA 2OEAB GND 1A15 1A14 1A17 2LEAB 1A16 n.c. 2A0 2A1 2A2 2A3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
MNA562
Fig.1 Pin configuration.
2000 Mar 16
4
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
74ALVCH32501
1OEAB 1CPBA 1LEBA 1CPAB 1LEAB 1OEBA
handbook, halfpage
VCC
data input
to internal circuit
C1 1A0
C1 1B0
MNA473
1D
1D
C1
C1
1D 18 IDENTICAL CHANNELS
1D
Fig.3 Bus-hold circuit.
2OEAB 2CPBA 2LEBA 2CPAB 2LEAB 2OEBA
C1 2A0
C1 2B0
1D
1D
C1
C1
1D 18 IDENTICAL CHANNELS
1D
MNA563
Fig.2 Logic symbol.
2000 Mar 16
5
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