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Details, datasheet, quote on part number:74AUP1G86GW
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| Part: | 74AUP1G86GW |
| Category: | Logic => Gates => EXOR/EXNOR Gates |
| Description: | Low-power 2-input EXCLUSIVE-OR gate
The 74AUP1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function.
Features
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114-C exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
Low static power consumption; ICC = 0.9 uA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 pct of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 Cel to +85Cel and -40 Cel to +125 Cel |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74AUP1G86GW datasheet File size : 86 kB |
| Request For quote: | Find where to buy 74AUP1G86GW
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