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Details, datasheet, quote on part number:74AVC16244DGG
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74AVC16244 16-bit buffer/line driver; 3-state (3.6 V tolerant)
Product specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC24 1999 Nov 15
Philips Semiconductors
Product specification
16-bit buffer/line driver; 3-state (3.6 V tolerant)
FEATURES · Wide supply voltage range from 1.2 to 3.6 V · Complies with JEDEC standard no. 8-1A/5/7 · CMOS low power consumption · Input/output tolerant up to 3.6 V · Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation · Low inductance multiple power and ground pins for minimum noise and ground bounce · Power off disables 74AVC16244 outputs, permitting live insertion. DESCRIPTION
74AVC16244
The 74AVC16244 is a 16-bit non-inverting buffer/line driver with 3-state outputs. This device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-state outputs are controlled by the output enable inputs nOE. A HIGH level on input nOE causes the outputs to assume a high-impedance OFF-state. This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, input nOE should be tied to VCC through a pull-up resistor (live insertion). A DCO circuitry is implemented to support termination line drive during transient (see Figs 1 and 2).
MNA506
handbook, halfpage
0
MNA507
handbook, halfpage
300
I OH (mA) 1.8 V -100
IOL (mA) 200 2.5 V 2.5 V
3.3 V
-200
100
1.8 V
3.3 V -300 0 0 1 2 3 VOH (V) 4 0 1 2 3 VOL (V) 4
Fig.1 Output current as a function of output voltage.
Fig.2 Output current as a function of output voltage.
1999 Nov 15
2
Philips Semiconductors
Product specification
16-bit buffer/line driver; 3-state (3.6 V tolerant)
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.0 ns; CL = 30 pF. SYMBOL tPHL/tPLH PARAMETER propagation delay nAn to nYn CONDITIONS VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CI CPD input capacitance power dissipation capacitance per buffer notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUTS nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. nAn L H X 34 1 2.6 1.8 1.7 1.3 1.1 5.0 TYP.
74AVC16244
UNIT ns ns ns ns ns pF pF pF
OUTPUTS nYn L H Z
1999 Nov 15
3
Philips Semiconductors
Product specification
16-bit buffer/line driver; 3-state (3.6 V tolerant)
ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74AVC16244DGG PINNING PIN 1 2, 3, 5 and 6 4, 10, 15, 21, 28, 34, 39 and 45 7, 18, 31 and 42 8, 9, 11 and 12 13, 14, 16 and 17 19, 20, 22 and 23 24 25 26, 27, 29 and 30 32, 33, 35 and 36 37, 38, 40 and 41 43, 44, 46 and 47 48 SYMBOL 1OE 1Y0 to 1Y3 GND VCC 2Y0 to 2Y3 3Y0 to 3Y3 4Y0 to 4Y3 4OE 3OE 4A3 to 4A0 3A3 to 3A0 2A3 to 2A0 1A3 to 1A0 2OE data outputs ground (0 V) positive supply voltage data outputs data outputs data outputs -40 to +85 °C PINS 48 PACKAGE TSSOP
74AVC16244
MATERIAL plastic
CODE SOT362-1
DESCRIPTION output enable input (active LOW)
output enable input (active LOW) output enable input (active LOW) data inputs data inputs data inputs data inputs output enable input (active LOW)
1999 Nov 15
4
Philips Semiconductors
Product specification
16-bit buffer/line driver; 3-state (3.6 V tolerant)
74AVC16244
handbook, halfpage
nA0
nY0
handbook, halfpage
1OE 1 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 2 3 4 5 6 7 8 9
48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 37 2A3
nA1
nY1
nA2
nY2
nA3
nY3
nOE
MNA502
GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24
MNA501
Fig.4 Logic symbol.
16244
36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE
handbook, halfpage
1 48 25 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN 2EN 3EN 4EN 1 1 2 3 5 6 12 8 9 11 12 13 13 14 16 17 14 19 20 22 23
MNA503
Fig.3 Pin configuration.
Fig.5 IEEE/IEC logic symbol.
1999 Nov 15
5
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