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Details, datasheet, quote on part number:74AVC16374
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| Part: | 74AVC16374 |
| Category: | Logic => Flip-Flops |
| Description: | 74AVC16374; 16-bit Edge Triggered D-type Flip-flop; 3.6 V Tolerant; 3-state;; Package: SOT362-1 (TSSOP48) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74AVC16374 datasheet File size : 94 kB |
| Request For quote: | Find where to buy 74AVC16374
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74AVC16374 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Product Specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC24 2000 Mar 09
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
FEATURES · Wide supply voltage range from 1.2 to 3.6 V · Complies with JEDEC standard no. 8-1A/5/7 · CMOS low power consumption · Input/output tolerant up to 3.6 V · DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation · Low inductance multiple VCC and GND pins to minimize noise and ground bounce · Supports Live Insertion. DESCRIPTION
74AVC16374
The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The 74AVC16374 consist of 2 sections of eight edge triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section. The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figs 1 and 2).
MNA506
handbook, halfpage
0
MNA507
handbook, halfpage
300
I OH (mA) 1.8 V -100
IOL (mA) 200 2.5 V 2.5 V
3.3 V
-200
100
1.8 V
3.3 V -300 0 0 1 2 3 VOH (V) 4 0 1 2 3 VOL (V) 4
Fig.1
Output voltage as a function of the HIGH-level output current.
Fig.2
Output voltage as a function of the LOW-level output current.
2000 Mar 09
2
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.0 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQn CONDITIONS VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V fmax maximum clock pulse frequency VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CI CPD input capacitance power dissipation capacitance per buffer notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUTS OPERATING MODES nOE Load and read register Load register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high impedance OFF-state; = LOW-to-HIGH CP transition. 2000 Mar 09 3 L L H H nCP nDn l h l h INTERNAL FLIP-FLOPS L H L H 66 1 3.1 2.4 2.0 1.5 1.3 250 300 320 350 350 5.0
74AVC16374
TYP. ns ns ns ns ns
UNIT
MHz MHz MHz MHz MHz pF pF pF
OUTPUTS nQn L H Z Z
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
ORDERING AND PACKAGE INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74AVC16374DGG PINNING PIN 1 2, 3, 5, 6, 8, 9, 11 and 12 4, 10, 15, 21, 28, 34, 39 and 45 7, 18, 31 and 42 13, 14, 16, 17, 19, 20, 22 and 23 24 25 26, 27, 29, 30, 32, 33, 35 and 36 37, 38, 40, 41, 43, 44, 46 and 47 48 1OE 1Q0 to 1Q7 GND VCC 2Q0 to 2Q7 2OE 2CP 2D7 to 2D0 1D7 to 1D0 1CP SYMBOL DESCRIPTION output enable input (active LOW) 3-state flip-flop outputs ground (0 V) DC supply voltage 3-state flip-flop outputs output enable input (active LOW) clock input data inputs data inputs clock input -40 to +85 °C PINS 48 PACKAGE TSSOP
74AVC16374
MATERIAL plastic
CODE SOT362-1
2000 Mar 09
4
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
74AVC16374
handbook, halfpage
1OE 1 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 2 3 4 5 6 7 8 9
48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 47 46 44 43 41 40 38
handbook, halfpage
1 1OE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1CP 48
24 2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2CP 25
MNA576
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
MNA575
16374
36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
37 36 35 33 32 30 29 27 26
Fig.3 Pin configuration.
Fig.4 Logic symbol.
2000 Mar 09
5
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