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Details, datasheet, quote on part number:74AVC16834ADGV
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| Part: | 74AVC16834ADGV |
| Category: | Logic => Buffers/Drivers |
| Description: | 74AVC16834A; 18-bit Registered Driver With Inverted Register Enable And Dynamic Controlled Outputs(TM) (3-State);; Package: SOT481-2 (TSSOP56) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74AVC16834ADGV datasheet File size : 125 kB |
| Request For quote: | Find where to buy 74AVC16834ADGV
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Datasheet text preview:
INTEGRATED CIRCUITS
74AVC16834A 18-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
Product data
Supersedes data of 2000 Jul 25
2002 Sep 11
Philips Semiconductors
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16834A
FEATURES
· Wide supply voltage range of 1.2 V to 3.6 V · Complies with JEDEC standard no. 8-1A/5/7 · CMOS low power consumption · Input/output tolerant up to 3.6 V · DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed degradation
PIN CONFIGURATION
NC NC Y0 GND Y1 Y2 VCC Y3 Y4 Y5 GND Y6 Y7 Y8 Y9 Y10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 CP GND
· Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
· Power off disables 74AVC16834A outputs, permitting Live · Integrated input diodes to minimize input overshoot and · Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292 undershoot Insertion
DESCRIPTION
The 74AVC16834A is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See the graphs on page 9 for typical curves.
Y11 GND Y12 Y13 Y14 VCC Y15 Y16 GND Y17 OE LE
SH00156
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.0 ns; CL = 30 pF. SYMBOL tPHL/tPLH PARAMETER Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation capacitance per buffer dissipation capacitance per buffer VI = GND to VCC1 GND to Outputs enabled Output disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CONDITIONS TYPICAL 2.6 2.0 1.7 2.9 2.3 1.9 5.0 25 6 UNIT ns
tPHL/tPLH CI CP D
ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic 0.5 mm pitch TSSOP 56-Pin Plastic 0.4 pitch TSSOP (TVSOP) TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C ORDER CODE 74AVC16834ADGG 74AVC16834ADGV DRAWING NUMBER SOT364-1 SOT481-2
2002 Sep 11
2
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16834A
PIN DESCRIPTION
PIN NUMBER 1, 2, 55 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 4, 11, 18, 25, 32, 39, 46, 53, 56 7, 22, 35, 50 27 28 30 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 SYMBOL NC Y0 to Y17 NAME AND FUNCTION No connection Data outputs
LOGIC SYMBOL
OE
GND VCC OE LE CP A0 to A17
Ground (0 V)
CP
Positive supply voltage Output enable input (active LOW) Latch enable input (active LOW) Clock input Data inputs
A1 D LE CP Y1 LE
TO THE 17 OTHER CHANNELS
SH00202
TYPICAL INPUT (DATA OR CONTROL)
VCC
A1
SH00200
2002 Sep 11
3
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16834A
LOGIC SYMBOL (IEEE/IEC)
OE CP LE 27 30 28 C3 G2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 1 3D 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 EN1 2C3
FUNCTION TABLE
INPUTS OE H L L L L L L H L X Z = = = = = LE X L L H H H H CP X X X H L A X L H L H X X OUTPUTS Z L H L H Y01 Y02
HIGH voltage level LOW voltage level Don't care High impedance "off" state LOW-to-HIGH level transition
NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established.
SH00158
168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE 74AVCM16834 74AVCM16834 74AVCM16834 PCK2509S or PCK2510S
The PLL clock distribution device and AVCM registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00407
2002 Sep 11
4
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable and Dynamic Controlled OutputsTM (3-State)
74AVC16834A
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage (according to JEDEC Low Voltage Standards) DC supply voltage (for low voltage applications) VI VO Tamb tr, tf DC Input voltage range DC output voltage range; output 3-State DC output voltage range; output HIGH or LOW state Operating free-air temperature range VCC = 1.65 to 2.3 V Input rise and fall times VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 1.65 2.3 3.0 1.2 0 0 0 40 0 0 0 MAX 1.95 2.7 3.6 3.6 3.6 3.6 VCC +85 30 20 10 ns/V UNIT V V V V °C
VCC
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output 3-State DC output voltage; output HIGH or LOW state DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic thin-medium-shrink (TSSOP) For temperature range: 40 to +125 °C above +55 °C derate linearly with 8 mW/K VI t0 For all inputs1 VO uVCC or VO t 0 Note 1 Note 1 VO = 0 to VCC CONDITIONS RATING 0.5 to +4.6 50 0.5 to 4.6 "50 0.5 to 4.6 0.5 to VCC +0.5 "50 "100 65 to +150 600 UNIT V mA V mA V V mA mA °C mW
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Sep 11
5
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