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Part: 74F154
Category:
Logic
-> Decoders/Demultiplexers
Description: 74F154; 1-of-16 Decoder/demultiplexer;; Package: SOT137 (SO24), SOT222-1 (DIP24)
Company: Philips Semiconductors
Datasheet: Download 74F154 datasheet File size : 93 kB
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INTEGRATED CIRCUITS
74F154 1-of-16 decoder/demultiplexer
Product specification IC15 Data Handbook 1990 Jan 08
Philips Semiconductors
Philips Semiconductors
Product specification
Decoder/demultiplexer
74F154
FEATURES
· 16-line demultiplexing capability · Mutually exclusive outputs · 2-input enable gate for strobing or expansion
DESCRIPTION
The 74F154 decoder accepts four active High binary address inputs and provides 16 mutually exclusive active Low outputs. The 2-input Enable (E0, E1) gate can be used to strobe the decoder to eliminate the normal decoding "glitches" on the outputs, or it can be used for expansion of the decoder. The enable gate has two AND'ed inputs which must be Low to enable the outputs. The 74F154 can be used as 1-of-16 demultiplexer by using one of the Enable inputs as the multiplexed data input. When the other Enable is Low, the addressed output will follow the state of the applied data. TYPICAL PROPAGATION DELAY 5.5 ns TYPICAL SUPPLY CURRENT (TOTAL) 26mA
ORDERING INFORMATION
DESCRIPTION 24-pin plastic Slim DIP (300mil) 24-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F154N N74F154D PKG DWG # SOT222-1 SOT137-1
PIN CONFIGURATION
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 13 VCC A0 A1 A2 A3 E0 E1 Q15 Q14 Q13 Q12 Q11
TYPE 74F154
Q8 Q9 Q10
GND 12
SF00681
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS A0 A3 E0, E1 Q0 Q15 Data inputs Enable inputs Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
23 22 21 20 Q0 A0 Q1 A1 A2 A3 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 18 19 VCC=Pin 24 GND=Pin 12 E1 E0 Q14 Q15 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17
LOGIC SYMBOL (IEEE/IEC)
DX 23 22 21 20 3 G 0 16 0 2 3 4 5 6 7 8 9 10 11 13 14 15 18 19 16 17 1
SF00680
SF00682
1990 Jan 08
2
8531155 98493
Philips Semiconductors
Product specification
Decoder/demultiplexer
74F154
LOGIC DIAGRAM
A0 E0 E1 A1 A2 A3
Q0 VCC = Pin 24 GND = Pin 12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
SF00683
FUNCTION TABLE
INPUTS E0 L H H L L L L L L L L L L L L L L L L E1 H L H L L L L L L L L L L L L L L L L A0 X X X L H L H L H L H L H L H L H L H A1 X X X L L H H L L H H L L H H L L H H A2 X X X L L L L H H H H L L L L H H H H A3 X X X L L L L L L L L H H H H H H H H Q0 H H H L H H H H H H H H H H H H H H H Q1 H H H H L H H H H H H H H H H H H H H Q2 H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H OUTPUTS Q3 Q4 H H H H H H H L H H H H H H H H H H H Q5 H H H H H H H H L H H H H H H H H H H Q6 H H H H H H H H H L H H H H H H H H H Q7 H H H H H H H H H H L H H H H H H H H Q8 H H H H H H H H H H H L H H H H H H H Q9 H H H H H H H H H H H H L H H H H H H Q10 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H OUTPUTS Q11 Q12 H H H H H H H H H H H H H H H L H H H Q13 H H H H H H H H H H H H H H H H L H H Q14 H H H H H H H H H H H H H H H H H L H Q15 H H H H H H H H H H H H H H H H H H L
H = High voltage level L = Low voltage level X = Don't care 1990 Jan 08 3
Philips Semiconductors
Product specification
Decoder/demultiplexer
74F154
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to VCC 40 0 to +70 65 to +150 UNIT V V mA V mA °C °C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 18 1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA °C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 CONDITIONS VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low-level output voltage output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) current (total) ICCH ICCL VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX VCC = MAX 60 26 35 ±10%VCC ±5%VCC ±10%VCC ±5%VCC LIMITS MIN 2.5 V 2.7 3.4 0.35 0.35 0.73 0.50 V 0.50 1.2 100 20 0.6 150 40 45 V µA µA mA mA mA mA TYP2 MAX UNIT
VOH
High-level output voltage output voltage
VOL VIK II IIH IIL IOS ICC
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1990 Jan 08
4
Philips Semiconductors
Product specification
Decoder/demultiplexer
74F154
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL Propagation delay An to Qn Propagation delay En to Qn Waveform 1 Waveform 2 2.0 3.5 2.0 4.0 TYP 5.0 6.5 4.0 6.0 MAX 9.5 10.0 7.5 9.0 VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500 MIN 1.5 3.0 1.5 3.5 MAX 10.5 10.5 8.0 9.5 ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V.
An
VM tPHL
VM tPLH
En
VM tPHL
VM tPLH
Qn
VM
VM
Qn,
VM
VM
SF00133
SF00684
Waveform 1. Propagation Delay for Address to Output
Waveform 2. Propagation Delay for Enable to Output
TEST CIRCUIT AND WAVEFORMS
V CC NEGATIVE PULSE V IN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tT H L 2.5ns
SF00006
1990 Jan 08
5
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