|
Details, datasheet, quote on part number:74F2373
| |
| Part: | 74F2373 |
| Category: | Logic => Latches |
| Description: | 74F2373; Octal Transparent Latch With 30 Ohm Equivalent Output Termination (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74F2373 datasheet File size : 97 kB |
| Request For quote: | Find where to buy 74F2373
|
| |
Datasheet text preview:
INTEGRATED CIRCUITS
74F2373 Octal transparent latch with 30 equivalent output termination (3-State)
Product specification Supersedes data of 1995 Jun 20 IC15 Data Handbook 1999 Feb 01
Philips Semiconductors
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
FEATURES
· 8-bit transparent latch · 30 Ohm output termination for driving DRAM · 3-State outputs glitch free during power-up and power-down · Common 3-State output register · Independent register and 3-State buffer operation
DESCRIPTION
The 74F2373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 30 Ohm series termination on the outputs reduces over/undershoot, making them ideal for driving DRAM
The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. When OE is high, the outputs are in high impedance "off " state, which means they will neither drive nor load the bus. TYPICAL PROPAGATION DELAY 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 35mA
TYPE 74F2373
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP 20-pin plastic SOL N74F2373N N74F2373D SOT146-1 SOT163-1 DRAWING NUMBER
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D7 E OE Q0 - Q7 Data inputs Enable input (active high) Output enable inputs (active low) 3-State outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 3.0mA/3.0mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 E
LOGIC SYMBOL
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 11 1 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 VCC = Pin 20 GND = Pin 10
5
6
9 12
15
16
19
SF00250
SF00251
1999 Feb 01
2
853-2140 20747
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
IEC/IEEE SYMBOL
1 11 EN1 EN2 2 5 6 9 12 15 16 19
3 4 7 8 13 14 17 18
2D
1
SF00252
LOGIC DIAGRAM
D0 3 D E E 11 D1 4 D E D2 7 D E D3 8 D E D4 13 D E D5 14 D E D6 17 D E D7 18 D E
Q
Q
Q
Q
Q
Q
Q
Q
OE
1 2 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
VCC = Pin 20 GND = Pin 10
Q0
SF00256
FUNCTION TABLE
INPUTS OE L L L L L H E H H L L Dn L H l h X X INTERNAL REGISTER L H L H NC NC OUTPUTS Q0 - Q7 L H L H NC Z Hold Disable outputs outputs Latch and read register and read register OPERATING MODE MODE
Enable and read register and read register
H H Dn Dn Z NOTES: H= High-voltage level h= High state must be present one setup time before the high-to-low enable transition L= Low-voltage level l= Low state must be present one setup time before the high-to-low enable transition NC = No change X= Don't care Z= High impedance "off " state = High-to-low enable transition
1999 Feb 01
3
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range 0.5 to +7.0 0.5 to +7.0 30 to +5 -0.5 to VCC 24 0 to +70 65 to +150 V V mA V mA °C °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIk IOH IOL Tamb * Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 18 3* 5* +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA
°C
12mA with reduced noise margin
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level output voltage output voltage VIH = MIN, IOH = 3mA VCC = MIN, VIL = MAX, VIH = MIN, IOH = 12mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 5mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 12mA VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX -60 ±10%VCC ±5%VCC ±10%VCC ±5%VCC ±10%VCC ±5%VCC ±10%VCC ±5%VCC MIN 2.4 2.7 2.0 2.0 0.42 0.42 0.67 0.67 -0.73 0.50 0.50 3.4 LIMITS TYP2 MAX UNIT V V V V V V V V V µA µA mA µA µA mA
VOL
Low-level output voltage out voltage
VIK II IIH IIL IOZH IOZL IOS
Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Short-circuit output current3
-1.2 100 20 -0.6 50 -50 -150
ICC Supply current (total) VCC = MAX 35 60 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1999 Feb 01
4
Philips Semiconductors
Product specification
Octal transparent latch with 30 equivalent output termination (3-State)
74F2373
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to high or low level Output disable time from high or low level Waveform 2 Waveform 1 Waveform 4 Waveform 5 Waveform 4 Waveform 5 3.0 2.0 5.0 3.0 2.0 2.0 2.0 2.0 TYP 5.3 3.7 9.0 4.0 5.0 5.6 4.5 3.8 MAX 8.0 6.0 12.0 8.0 12.0 8.0 6.5 5.5 VCC = +5.0V ± 10% CL = 50pF, RL = 500 MIN 3.0 2.0 5.0 3.0 2.0 2.0 2.0 2.0 MAX 9.0 7.0 12.5 8.5 12.5 8.5 7.5 6.5 ns ns ns ns Tamb = 0°C to +70°C UNIT
AC SETUP REQUIREMENTS
LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) Setup time, high or low level Dn to E Hold time, high or low level Dn to E E Pulse width, high Waveform 3 Waveform 3 Waveform 1 0 1.0 3.0 3.0 3.5 TYP MAX VCC = +5.0V ± 10% CL= 50pF, RL = 500 MIN 0 1.0 3.0 3.0 4.0 MAX ns ns ns Tamb = 0°C to +70°C UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
tw(H) E VM tPHL Qn VM VM VM tPLH VM
Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
E
VM
VM
SF00261 SF00259
Waveform 3. Data setup time and hold times
Waveform 1. Propagation delay for enable to output and enable pulse width
Dn
OEn VM tPLH VM tPHL Qn, Qn
VM tPZH VM
VM tPHZ VOH -0.3V
Qn
VM
VM
0V
SF00260
SF00263
Waveform 2. Propagation delay for data to output
Waveform 4. 3-State output enable time to high level and output disable time from high level
1999 Feb 01
5
|
|
