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Part: 74F377A
Category:
Logic
-> Flip-Flops
-> Bipolar->F Family
Description: 74F377A; Octal D-type Flip-flop With Enable
Company: Philips Semiconductors
Datasheet: Download 74F377A datasheet File size : 222 kB
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INTEGRATED CIRCUITS
74F377A Octal D-type flip-flop with enable
Product specification IC15 Data Handbook 1996 Mar 12
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
FEATURES
High states)
· High impedance inputs for reduced loading (20µA in Low and · Ideal for addressable register applications · Enable for address and data synchronization applications · Eight edgetriggered Dtype flipflops · Buffered common clock · See 'F273A for Master Reset version · See 'F373 for transparent latch version · See 'F374 for 3State version
TYPE 74F377A TYPICAL fMAX 165MHz
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
TYPICAL SUPPLY CURRENT (TOTAL) 29mA
ORDERING INFORMATION
PACKAGES 20pin plastic DIP 20pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C N74F377AN N74F377AD PKG. DWG. # SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FANOUT TABLE
PINS D0 D7 CP E Q0 Q7 Data inputs Clock pulse input (active rising edge) Enable input (activeLow) Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 1.0mA/20mA
PIN CONFIGURATION
E Q0 1 2 20 VCC 19 Q7 18 D7
LOGIC SYMBOL
3 4 7 8 13 14 17 18
D0 3 D1 4 Q1 Q2 5 6
D0 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP VCC = Pin 20 GND = Pin 10 2 Q0 11 1 D2 7 D3 8 Q3 9 CP E
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
5
6
9
12
15
16
19
GND 10
SF00350
SF00351
1996 Mar 12
2
8530026 16555
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
LOGIC SYMBOL (IEEE/IEC)
1 11 G1
FUNCTION TABLE
INPUTS E CP Dn h l OUTPUTS Qn H L Load "1" Load "0" OPERATING MODE
1C2
l
3 4 7 8 13 14 17 18 2D 2 5 6 9 12 15 16 19
l
h X no change Hold (do nothing) H X X no change H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition
SF00352
LOGIC DIAGRAM
D0 3 1 E D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 18 D7
D CP 11
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
CP
2 Q0 VCC = Pin 20 GND = Pin 10
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
SF00353
1996 Mar 12
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to VCC 40 0 to +70 65 to +150 UNIT V V mA V mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage Highlevel input voltage Lowlevel input voltage Input clamp current Highlevel output current Lowlevel output current Operating free air temperature range 0 4.5 2.0 0.8 18 1 20 +70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA UNIT
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 E & CP inputs VOH High-level output voltage Other inputs VCC = MIN, VIL = 0.0V3, ±10%VCC ±5%VCC ±10%VCC ±5%VCC ±10%VCC ±5%VCC MIN 2.5 2.7 2.5 2.7 0.35 0.35 0.73 0.50 0.50 -1.2 100 20 20 60 27 150 40 3.4 LIMITS TYP2 MAX V V V V V V V µA µA µA mA mA UNIT
VIH = 4.5V3, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX ICCH VCC = MAX MAX
VOL VIK II IIH IIL IOS ICC
Low-level output voltage
Input clamp voltage Input current at maximum input voltage Highlevel input current Lowlevel input current Short circuit output current4
Supply current (total) current (total)
ICCL VCC = MAX 29 43 mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. To reduce the effect of external noise during test. Special test conditions are not necessary for the '377A. 4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1996 Mar 12
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
AC CHARACTERISTICS
LIMITS Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500 MIN fMAX tPLH tPHL Maximum clock frequency Propagation delay CP to Qn 1 1 150 3.0 4.5 TYP 165 5.0 6.5 8.0 9.0 MAX Tamb =0oC to +70oC VCC = +5.0V ±10% CL = 50pF RL = 500 MIN 120 2.5 4.0 9.0 10.5 MAX MHz ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
AC SETUP REQUIREMENTS
LIMITS Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low E to CP Hold time, High or Low E to CP Clock Pulse width High or Low 2 2 2 2 1 2.5 2.5 1.0 0.0 3.0 4.0 0.0 0.0 4.0 4.0 TYP MAX Tamb = 0oC to +70oC VCC = +5.0V ±10% CL = 50pF RL = 500 MIN 2.5 2.5 1.0 0.0 3.0 4.5 0.0 0.0 5.0 4.0 MAX ns ns ns ns ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
AC WAVEFORMS
1/fmax Dn CP VM tw(H) tPHL VM tw(L) tPLH VM ts VM VM th VM VM
Qn
E
VM
VM th = 0
VM
VM th = 0
SF00294
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width and Maximum Clock Frequency
CP NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
ts(L) VM
ts(H) VM
SF01237
Waveform 2. Data and Enable Setup and Hold Times
1996 Mar 12
5
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