Digchip : Database on electronics components
Electronics components database

Details, datasheet, quote on part number: 74F377A
Part number74F377A
CategoryLogic => Flip-Flops => Bipolar->F Family
TitleBipolar->F Family
Description74F377A; Octal D-type Flip-flop With Enable
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F377A datasheet
Request For QuoteFind where to buy 74F377A

Specifications, Features, Applications


· High impedance inputs for reduced loading (20µA in Low and· Ideal for addressable register applications· Enable for address and data synchronization applications· Eight edge­triggered D­type flip­flops· Buffered common clock· See 'F273A for Master Reset version· See 'F373 for transparent latch version· See 'F374 for 3­State version


The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

PACKAGES 20­pin plastic DIP 20­pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb N74F377AN N74F377AD PKG. DWG. SOT146-1 SOT163-1

PINS ­ Q7 Data inputs Clock pulse input (active rising edge) Enable input (active­Low) Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/20µA 1.0mA/20mA


X no change Hold (do nothing) X no change H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition

Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74F378 74F378; Hex D Flip-flop With Enable
74F379A 74F379A; Quad Register;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F38 74F38; Quad 2-input NAND Buffer (open Collector);; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F381 Arithmetic Logic Unit
74F382 74F382; Arithmetic Logic Unit
74F385 Quad Serial Adder/subtractor
74F3893 Quad Futurebus Backplane Transceiver
74F393 74F393; Dual 4-bit Binary Ripple Counter;; Package: SOT27-1 (DIP14)
74F395 4-bit Cascadable Shift Register (3-state)
74F399 74F399; Quad 2-port Register;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F40 74F40; Dual 4-input NAND Buffer
74F455 Buffers/drivers
74F456 74F456; Octal Buffer/driver With Parity, Non-inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)
74F50109 74F50109; Synchronizing Dual J-k Positive Edge-triggered Flip-flop With Metastable Immune Characteristics;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F50728 74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F50729 74F50729; Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics;; Package: SOT27-1 (DIP14)
74F5074 74F5074; Synchronizing Dual D-type Flip-flop/clock Driver;; Package: SOT27-1 (DIP14)
74F51 74F51; Dual 2-wide 2-input, 2-wise 3-input And-or-invert Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F521 74F521; 8-bit Identity Comparator;; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F524 74F524; 8-bit Register Comparator (open-collector + 3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)