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Details, datasheet, quote on part number: 74F377A
Part74F377A
CategoryLogic => Flip-Flops => Bipolar->F Family
TitleBipolar->F Family
Description74F377A; Octal D-type Flip-flop With Enable
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F377A datasheet
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Features, Applications

FEATURES

High impedance inputs for reduced loading (20µA in Low and Ideal for addressable register applications Enable for address and data synchronization applications Eight edge­triggered D­type flip­flops Buffered common clock See 'F273A for Master Reset version See 'F373 for transparent latch version See 'F374 for 3­State version

DESCRIPTION

The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

PACKAGES 20­pin plastic DIP 20­pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb N74F377AN N74F377AD PKG. DWG. SOT146-1 SOT163-1

PINS ­ Q7 Data inputs Clock pulse input (active rising edge) Enable input (active­Low) Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/20µA 1.0mA/20mA


INPUTS h l OUTPUTS H L Load "1" Load "0" OPERATING MODE

X no change Hold (do nothing) X no change H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition



 

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