Details, datasheet, quote on part number: 74F377A
Part74F377A
CategoryLogic => Flip-Flops => Bipolar->F Family
TitleBipolar->F Family
Description74F377A; Octal D-type Flip-flop With Enable
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F377A datasheet
Quote
Find where to buy
 
  

 

Features, Applications

FEATURES

High impedance inputs for reduced loading (20µA in Low and Ideal for addressable register applications Enable for address and data synchronization applications Eight edge­triggered D­type flip­flops Buffered common clock See 'F273A for Master Reset version See 'F373 for transparent latch version See 'F374 for 3­State version

DESCRIPTION

The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

PACKAGES 20­pin plastic DIP 20­pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb N74F377AN N74F377AD PKG. DWG. SOT146-1 SOT163-1

PINS ­ Q7 Data inputs Clock pulse input (active rising edge) Enable input (active­Low) Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/20µA 1.0mA/20mA


INPUTS h l OUTPUTS H L Load "1" Load "0" OPERATING MODE

X no change Hold (do nothing) X no change H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition X = Don't care = Low-to-High clock transition



 

Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74F378 74F378; Hex D Flip-flop With Enable
74F379A 74F379A; Quad Register;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F38 74F38; Quad 2-input NAND Buffer (open Collector);; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F381 Arithmetic Logic Unit
74F382 74F382; Arithmetic Logic Unit
74F385 Quad Serial Adder/subtractor
74F3893 Quad Futurebus Backplane Transceiver
74F3893A
74F393 74F393; Dual 4-bit Binary Ripple Counter;; Package: SOT27-1 (DIP14)
74F395 4-bit Cascadable Shift Register (3-state)
74F399 74F399; Quad 2-port Register;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F40 74F40; Dual 4-input NAND Buffer
74F455 Buffers/drivers
74F456 74F456; Octal Buffer/driver With Parity, Non-inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)
74F50109 74F50109; Synchronizing Dual J-k Positive Edge-triggered Flip-flop With Metastable Immune Characteristics;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F50728 74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F50729 74F50729; Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics;; Package: SOT27-1 (DIP14)
74F5074 74F5074; Synchronizing Dual D-type Flip-flop/clock Driver;; Package: SOT27-1 (DIP14)
74F51 74F51; Dual 2-wide 2-input, 2-wise 3-input And-or-invert Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F521 74F521; 8-bit Identity Comparator;; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F524 74F524; 8-bit Register Comparator (open-collector + 3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
Same catergory

10371QC : Low Power Triple 4-input Multiplexer With Enable. The 100371 contains three 4-input multiplexers which share a common decoder (inputs S0 and S1). Output buffer gates provide true and complement outputs. A HIGH on the Enable input (E) forces all true outputs LOW (see Truth Table). All inputs have 50 k pull-down resistors. s 35% power reduction of the s 2000V ESD protection s Pin/function compatible.

54ACT821F : 10-bit D Flip-flop With Tri-state Outputs. The 10-bit D flip-flop with TRI-STATE outputs arranged in a broadside pinout. The 'AC/'ACT821 is functionally identical to the AM29821. Noninverting outputs Outputs source/sink mA 'ACT821 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'AC821: 5962-91606 Data Inputs Data Outputs Output Enable Input Clock Input TRI-STATE is a registered.

54LS175DMQB : Hex/quad D Flip-flops With Clear. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse Clock.

74LVC162244A : 3.3V CMOS 16-BIT Buffer/driver With 3-STATE Outputs, 5V Tolerant I/O, And Bus-hold.

CD74HC165E : ti CD74HC165, High Speed CMOS Logic 8-Bit Parallel-in/serial-out Shift Register.

DM54LS240 : Military/Aerospace->Low Power Schottky. DM54LS240 - Octal Tri-state Buffer/line Driver/line Receiver (Inverting), Package: Lcc, Pin Nb=20.

DM96L02 : Bipolar->TTL Family. Dual Retriggerable Resettable Monostable Multivibrator.

HCC4072BC1 : OR GATE. 4071B - QUAD 2­INPUT OR GATE 4072B - QUAD 4­INPUT OR GATE 4075B - TRIPLE 3­INPUT OR GATE MEDIUM-SPEED OPERATION tPLH, tPHL = 60ns. (typ.) AT VDD = 10V QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE 5V, 10V AND 15V PARAMETRIC RATINGS INPUT CURRENT AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE.

HCF4096 : HCF->CMOS 4000B Series. Gate J-k Master-slave Flip-flops. 16MHz TOGGLE RATE (Typ.) at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT = 100nA (MAX) AT VDD 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD S FOR OF B SERIES CMOS DEVICES" is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor.

JM38510/30102B2A : D-Type Flip-Flops. ti SN54LS74A, Dual D-type Positive-edge-triggered Flip-flops With Preset And Clear.

SN54LVTH162244WD : 3.3-v Abt 16-bit Buffers/drivers With 3-state Outputs. Members of the Texas Instruments Widebus TM Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated.

SN64BCT29828BDW : Inverting Buffers and Drivers. ti SN64BCT29828B, 10-Bit Buffers And Bus Drivers.

SN74ACT72221L15RJ : Synchronous FIFOs. ti SN74ACT72221L, 1KX9memory. Read and Write Clocks Can Be Asynchronous or Coincident Organization: SN74ACT72231L SN74ACT72241L Write and Read Cycle Times 15 ns Bit-Width Expandable Empty and Full Flags Programmable Almost-Empty and Almost-Full Flags With Default Offsets of Empty+7 and Full ­7, Respectively TTL-Compatible Inputs Fully Compatible With the IDT72211 Available in 32-Pin.

SN74ALVC244DGV : Octal Buffer/driver With 3-state Outputs. EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model = 200 pF, = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW, NS), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages.

SN74CBTLVR16292DL : Bus Exchange/Multiplexing Switches. ti SN74CBTLVR16292, Low-voltage 12-Bit 1-of-2 Fet Multiplexer/demultiplexer With Internal Pulldown Resistors.

SN74HC165 : CMOS/BiCMOS->HC/HCT Family. 8-bit Parallel-in/serial-out Shift Register.

TC74AC240FT : TC74AC Series. Function = Octal Bus Buffer (3-state/inv.) ;; Pins = 20.

SC68C652B : 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and Motorola uP interface The SC68C652B is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data.

 
0-C     D-L     M-R     S-Z