|Category||Logic => Flip-Flops => Bipolar->F Family|
|Description||74F378; Hex D Flip-flop With Enable|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F378 datasheet
6-bit high-speed parallel register Positive edge-triggered D-type inputs Fully buffered common Clock and Enable inputs Input clamp diodes limit high speed termination effects Fully TTL and CMOS compatibleDESCRIPTION
The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
PINS CP E Data inputs Clock pulse input (active rising edge) Enable input (active low) DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA
Q5 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.INPUTS h l OUTPUTS H L OPERATING MODE Load "1" Load "0" Hold (do nothing)
X no change X no change High-voltage level High-voltage level one setup time prior to the Low-to-High clock transition Low-voltage level Low-voltage level one setup time prior to the Low-to-High clock transition Don't care Low-to-High clock transition
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