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Part: 74F378
Category:
Logic
-> Flip-Flops
-> Bipolar->F Family
Description: 74F378; Hex D Flip-flop With Enable
Company: Philips Semiconductors
Datasheet: Download 74F378 datasheet File size : 222 kB
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INTEGRATED CIRCUITS
74F378 Hex D flip-flop with enable
Product specification IC15 Data Handbook 1989 Oct 05
Philips Semiconductors
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
FEATURES
· 6-bit high-speed parallel register · Positive edge-triggered D-type inputs · Fully buffered common Clock and Enable inputs · Input clamp diodes limit high speed termination effects · Fully TTL and CMOS compatible
DESCRIPTION
The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop's Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
TYPE 74F378
TYPICAL fmax 100MHz
TYPICAL SUPPLY CURRENT (TOTAL) 35mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F378N N74F378D PKG DWG #
16pin plastic DIP 16pin plastic SO
SOT38-4 SOT109-1
PIN CONFIGURATION
E1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 16 V CC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP
SF00927
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 D5 CP E Data inputs Clock pulse input (active rising edge) Enable input (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA
Q0 Q5 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Oct 05
2
8530067 97804
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
LOGIC SYMBOL
3 4 6 11 13 14
IEC/IEEE SYMBOL
1 9 3 2D 4 6 Q0 Q1 Q2 Q3 Q4 Q5 11 13 2 5 7 10 12 15 14 15 10 12 G1 1C2 2 5 7
D0 D1 D2 D3 D4 D5 9 1 CP E
VCC = Pin 16 GND = Pin 8
SF00916
SF00917
LOGIC DIAGRAM
D0 3 E 1 D1 4 D2 6 D3 11 D4 13 D5 14
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
CP
9 2 Q0 Q1 5 Q2 7 Q3 10 Q4 12 Q5 15
VCC = Pin 16 GND = Pin 8
SF00918
FUNCTION TABLE
INPUTS E l l h H H= h= L= l= X= = CP Dn h l OUTPUTS Qn H L OPERATING MODE Load "1" Load "0" Hold (do nothing)
X no change X X no change High-voltage level High-voltage level one setup time prior to the Low-to-High clock transition Low-voltage level Low-voltage level one setup time prior to the Low-to-High clock transition Don't care Low-to-High clock transition
1989 Oct 05
3
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to VCC 40 0 to +70 65 to +150 UNIT V V mA V mA
°C °C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARMETER SYMBOL MIN 4.5 2.0 0.8 18 1 20 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level output voltage output voltage VIH = MIN, IOH = MAX Low-level output voltage output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 ICCH VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX MAX 60 32 ±10%VCC ±5%VCC ±10%VCC ±5%VCC MIN 2.5 2.7 3.4 0.30 0.30 0.73 0.50 0.50 1.2 100 20 0.6 150 45 LIMITS TYP2 MAX V V V V V µA µA mA mA mA UNIT
VOL VIK II IIH IIL IOS ICC
Supply current (total) current (total)
ICCL 35 45 mA Notes: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1989 Oct 05
4
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Waveform 1 Waveform 1 Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL Maximum clock frequency Propagation delay CP to Qn 80 3.0 3.5 TYP 100 5.5 6.0 7.5 8.5 MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500 MIN 80 3.0 3.5 8.5 9.5 MAX MHz ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500 MIN ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low E to CP Hold time, High or Low E to CP CP Pulse width, High or Low Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 1 4.0 4.0 0 0 4.0 10.0 0 0 4.0 6.0 TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL= 50pF, RL = 500 MIN 4.0 4.0 0 0 4.0 10.0 0 0 4.0 6.0 MAX ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP Dn VM tw(H) tPHL VM tw(L) tPLH En Qn VM ts(L) th=0 VM ts(H) th=0 VM VM VM VM VM VM VM VM ts VM th
SF00919
CP
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF00920
Waveform 2. Data and Enable Setup Time and Hold Times
1989 Oct 05
5
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