· Edge­triggered D­type inputs· Buffered positive edge­triggered clock· Buffered common enable input· True and complementary outputs· Offers light loading PNP inputs (IIL = ­20µA)

The a 4­bit register with buffered common enable (E). This device is similar to the 74F175A but features the common enable rather than common master reset.

ORDER CODE DESCRIPTION 16­pin plastic DIP 16­pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F379AN N74F379AD PKG, DWG. SOT38­4 SOT109­1

TYPE PINS ­ Q3 Data inputs Clock pulse input (active rising edge) Enable input (active low) True outputs DESCRIPTION 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/LOW 1.0mA/20mA 15mA/20mA

­ Q3 Complementary outputs Note to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

l L Notes to function table H = High­voltage level h = High state must be present one setup time before the low­to­high clock transition L = Low­voltage level l = Low state must be present one setup time before the low­to­high clock transition NC= No change X = Don't care = Low­to­high clock transition